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FSDH321

型  号:
FSDH321
大  小:
935.57KB 共22页
厂  商:
FAIRCHILD[FairchildSemiconductor]
主  页:
http://www.fairchildsemi.com/
功能介绍:
FSDH321 - Green Mode Fairchild Power Switch (FPSTM) - Fairchild Semiconductor
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www.fairchildsemi.com FSDL0365RN, FSDM0365RN Features • Internal Avalanche Rugged Sense FET • Consumes only 0.65W at 240VAC & 0.3W load with Advanced Burst-Mode Operation • Frequency Modulation for low EMI • Precision Fixed Operating Frequency • Internal Start-up Circuit • Pulse by Pulse Current Limiting • Abnormal Over Current Protection • Over Voltage Protection • Over Load Protection • Internal Thermal Shutdown Function • Auto-Restart Mode • Under Voltage Lockout • Low Operating Current (3mA) • Adjustable Peak Current Limit • Built-in Soft Start Green Mode Fairchild Power Switch (FPSTM) OUTPUT POWER TABLE 230VAC ±15%(3) PRODUCT FSDL321 FSDH321 FSDL0165RN FSDM0265RN FSDH0265RN FSDL0365RN FSDM0365RN FSDL0165RL FSDM0265RL FSDH0265RL FSDL0365RL FSDM0365RL Adapter(1) 11W 11W 13W 16W 16W 19W 19W 13W 16W 16W 19W 19W Open Frame(2) 17W 17W 23W 27W 27W 30W 30W 23W 27W 27W 30W 30W 85-265VAC Adapter(1) 8W 8W 11W 13W 13W 16W 16W 11W 13W 13W 16W 16W Open Frame(2) 12W 12W 17W 20W 20W 24W 24W 17W 20W 20W 24W 24W Applications • SMPS for VCR, SVR, STB, DVD & DVCD • SMPS for Printer, Facsimile & Scanner • Adaptor for Camcorder Description The FSDx0365RN(x stands for L, M) are integrated Pulse Width Modulators (PWM) and Sense FETs specifically designed for high performance offline Switch Mode Power Supplies (SMPS) with minimal external components. Both devices are integrated high voltage power switching regulators which combine an avalanche rugged Sense FET with a current mode PWM control block. The integrated PWM controller features include: a fixed oscillator with frequency modulation for reduced EMI, Under Voltage Lock Out (UVLO) protection, Leading Edge Blanking (LEB), optimized gate turn-on/turn-off driver, Thermal Shut Down (TSD) protection, Abnormal Over Current Protection (AOCP) and temperature compensated precision current sources for loop compensation and fault protection circuitry. When compared to a discrete MOSFET and controller or RCC switching converter solution, the FSDx0365RN reduce total component count, design size, weight and at the same time increase efficiency, productivity, and system reliability. Both devices are a basic platform well suited for cost effective designs of flyback converters. Table 1. Notes: 1. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient. 2. Maximum practical continuous power in an open frame design at 50°C ambient. 3. 230 VAC or 100/115 VAC with doubler. Typical Circuit AC IN DC OUT Vstr Ipk PWM Vfb Drain Vcc Source Figure 1. Typical Flyback Application Rev.1.0.4 ©2004 Fairchild Semiconductor Corporation FSDL0365RN, FSDM0365RN Internal Block Diagram Vcc 2 + Vstr 5 Drain 6,7,8 Istart Soft start V BURL /V BURH - 8V/12V V BURH Vcc I B_PEAK Vcc I delay Vcc Vcc good Freq. Modulation Vref Internal Bias OSC V FB 3 I FB Normal S Q PWM Burst R Q 2.5R Ipk 4 R Gate driver LEB V SD Vcc S Q 1 GND AOCP Vocp Vovp TSD Vcc good R Q Figure 2. Functional Block Diagram of FSDx0365RN 2 FSDL0365RN, FSDM0365RN Pin Definitions Pin Number 1 Pin Name GND Pin Function Description Sense FET source terminal on primary side and internal control ground. Positive supply voltage input. Although connected to an auxiliary transformer winding, current is supplied from pin 5 (Vstr) via an internal switch during startup (see Internal Block Diagram section). It is not until Vcc reaches the UVLO upper threshold (12V) that the internal start-up switch opens and device power is supplied via the auxiliary transformer winding. The feedback voltage pin is the non-inverting input to the PWM comparator. It has a 0.9mA current source connected internally while a capacitor and optocoupler are typically connected externally. A feedback voltage of 6V triggers over load protection (OLP). There is a time delay while charging between 3V and 6V using an internal 5uA current source, which prevents false triggering under transient conditions but still allows the protection mechanism to operate under true overload conditions. Pin to adjust the current limit of the Sense FET. The feedback 0.9mA current source is diverted to the parallel combination of an internal 2.8kΩ resistor and any external resistor to GND on this pin to determine the current limit. If this pin is tied to Vcc or left floating, the typical current limit will be 2.15A. This pin connects directly to the rectified AC line voltage source. At start up the internal switch supplies internal bias and charges an external storage capacitor placed between the Vcc pin and ground. Once the Vcc reaches 12V, the internal switch is disabled. The Drain pin is designed to connect directly to the primary lead of the transformer and is capable of switching a maximum of 650V. Minimizing the length of the trace connecting this pin to the transformer will decrease leakage inductance. 2 Vcc 3 Vfb 4 Ipk 5 Vstr 6, 7, 8 Drain Pin Configuration 8DIP 8LSOP GND 1 Vcc 2 Vfb 3 Ipk 4 8 Drain 7 Drain 6 Drain 5 Vstr Figure 3. Pin Configuration (Top View) 3 FSDL0365RN, FSDM0365RN Absolute Maximum Ratings (Ta=25°C, unless otherwise specified) Characteristic Drain Current Pulsed (1) Symbol IDM Energy(2) EAS VCC,MAX VFB PD TJ TA TSTG Value 12.0 127 20 -0.3 to VSD 1.56 +150 -25 to +85 -55 to +150 Unit ADC mJ V V W °C °C °C Single Pulsed Avalanche Maximum Supply Voltage Analog Input Voltage Range Total Power Dissipation Operating Junction Temperature. Operating Ambient Temperature. Storage Temperature Range. Note: 1. Repetitive rating: Pulse width limited by maximum junction temperature 2. L = 51mH, starting Tj = 25°C 3. L = 13µH, starting Tj = 25°C 4. Vsd is shutdown feedback voltage ( see Protection Section in Electrical Characteristics ) Thermal Impedance Parameter 8DIP Junction-to-Ambient Thermal Junction-to-Case Thermal Symbol Value 85.74 30.38 Unit °C/W(3) °C/W θJA(1) θJC(2) Note: 1. Free standing with no heatsink. 2. Measured on the GND pin close to plastic interface. 3. Soldered to 0.36 sq. inch(232mm2), 2 oz.(610g/m2) copper clad. 4 FSDL0365RN, FSDM0365RN Electrical Characteristics (Ta = 25°C unless otherwise specified) Parameter Sense FET SECTION Startup Voltage (Vstr) Breakdown Drain-Source Breakdown Voltage Off-State Current (Max.Rating =660V) On-State Resistance(1) Symbol Condition Min. Typ. Max. Unit BVSTR BVDSS IDSS RDS(ON) CISS COSS CRSS TD(ON) TR TD(OFF) TF VCC=0V, ID=1mA VGS=0V, ID=50µA VDS=660V, VGS=0V VDS=0.8Max.Rating, VGS=0V, TC=125°C VGS=10V, ID=0.5A VGS=0V, VDS=25V, F=1MHz 650 650 - 3.6 315 47 9 11.2 34 28.2 32 50 200 4.5 - V V µA µA Ω Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn On Delay Time Rise Time Turn Off Delay Time Fall Time CONTROL SECTION Output Frequency Output Frequency Modulation Output Frequency Output Frequency Modulation Frequency Change With Temperature(2) pF pF pF ns ns ns ns VDS=325V, ID=1.0A (Sense FET switching time is essentially independent of operating temperature) - FOSC FMOD FOSC FMOD DMAX DMIN VSTART VSTOP IFB TS/S 61 FSDM0365R ±1.5 45 FSDL0365R -25°C ≤ Ta ≤ 85°C ±1.0 71 0 VFB=GND VFB=GND VFB=GND VFB=4V 11 7 0.7 10 67 ±2.0 50 ±1.5 ±5 77 0 12 8 0.9 15 73 ±2.5 55 ±2.0 ±10 83 0 13 9 1.1 20 KHz KHz KHz KHz % % % V V mA ms Maximum Duty Cycle Minimum Duty Cycle Start threshold voltage Stop threshold voltage Feedback Source Current Internal Soft Start Time BURST MODE SECTION Burst Mode Voltages PROTECTION SECTION Drain to Source Peak Current Limit VBURH VBURL - 0.4 0.25 0.5 0.35 0.6 0.45 V V IOVER Max. inductor current 1.89 2.15 2.41 A 5 FSDL0365RN, FSDM0365RN Current Limit Delay(3) Thermal Shutdown Shutdown Feedback Voltage Over Voltage Protection Shutdown Feedback Delay Current Leading Edge Blanking Time TOTAL DEVICE SECTION Operating Current Start Up Current Vstr Supply Voltage TCLD TSD VSD VOVP IDELAY TLEB VFB=4V - 125 5.5 18 3.5 200 500 140 6.0 19 5.0 - 6.5 6.5 - ns °C V V µA ns IOP ISTART VSTR VCC=14V VCC=0V VCC=0V 1 0.7 35 3 0.85 - 5 1.0 - mA mA V Note: 1. Pulse test: Pulse width ≤ 300uS, duty ≤ 2% 2. These parameters, although guaranteed, are tested in EDS (wafer test) process 3. These parameters, although guaranteed, are not 100% tested in production 6 FSDL0365RN, FSDM0365RN Comparison Between KA5x0365RN and FSDx0365RN Function Soft-Start KA5x0365RN not applicable FSDx0365RN 15mS FSDx0365RN Advantages • Gradually increasing current limit during soft-start further reduces peak current and voltage component stresses • Eliminates external components used for soft-start in most applications • Reduces or eliminates output overshoot • Smaller transformer • Allows power limiting (constant overload power) • Allows use of larger device for lower losses and higher efficiency. • Reduced conducted EMI • Improve light load efficiency • Reduces no-load consumption • Transformer audible noise reduction • Greater immunity to arcing as a result of build-up of dust, debris and other contaminants External Current Limit not applicable Programmable of default current limit Frequency Modulation Burst Mode Operation not applicable not applicable ±2.0KHz @67KHz ±1.5KHz @50KHz Yes-built into controller 7.62mm Drain Creepage at Package 1,02mm 7 FSDL0365RN, FSDM0365RN Typical Performance Characteristics (Sense FET part) 10 1 ID, Drain Current [A] 10 0 VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V Bottom : 5.5 V Top : 10 -1 ※ Note : 1. 250µs Pulse Test 2. TC = 25℃ 10 0 10 1 VDS, Drain-Source Voltage [V] Output Characteristics 8.0 IDR , Reverse Drain Current [A] 7.5 RDS(ON) [Ω ], Drain-Source On-Resistance 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 0 1 2 3 4 ※ Note : TJ = 25℃ 10 1 VGS = 10V VGS = 20V 10 0 150℃ 25℃ ※ Note : 1. VGS = 0V 2. 250µ s Pulse Test 5 6 7 10 -1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ID, Drain Current [A] VSD , Source-Drain Voltage [V] On-Resistance vs. Drain Current 700 600 500 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd Source-Drain Diode Forward Voltage 12 Ciss Coss VGS, Gate-Source Voltage [V] 10 VDS = 130V V DS = 325V Capacitances [pF] 8 400 300 200 100 VDS = 520V 6 Crss ※ Note ; 1. VGS = 0 V 2. f = 1 MHz 4 2 ※ N ote : ID = 3.0 A 10 -1 10 0 10 1 0 0 2 4 6 8 10 12 VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC] Capacitance vs. Drain-Source Voltage Gate Charge vs. Gate-Source Voltage 8 FSDL0365RN, FSDM0365RN Typical Performance Characteristics (Continued) 1.15 BVDSS, (Normalized) Drain-Source Breakdown Voltage 2.5 1.10 RDS(ON), (Normalized) Drain-Source On-Resistance 2.0 1.05 1.00 1.5 0.95 ※ Note : 1. VGS = 0 V 2. ID = 250 µ A 1.0 ※ Note : 1. VGS = 10 V 2. ID = 1.5 A 0.90 -50 0 50 100 o 0.5 -50 0 50 100 o 150 150 TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Breakdown Voltage vs. Temperature On-Resistance vs. Temperature 2.0 10 1 Operation in This Area is Limited by R DS(on) 10 µs ID, Drain Current [A] 10 -1 DC 10 s 1s 10 ms 100 ms 1 ms ID, Drain Current [A] 10 0 100 µs 1.5 1.0 10 -2 0.5 10 -3 10 0 10 1 10 2 0.0 25 50 75 100 125 150 VDS, Drain-Source Voltage [V] TC, Case Temperature [℃] Max. Safe Operating Area Max. Drain Current vs. Case Temperature 0.2 D=0.5 0.2 Zθ JC(t), Thermal Response 10 0.1 0.05 0.02 1 0.01 ※ Notes : 1. Zθ JC(t) = 80 ℃/W Max. 2. Duty Factor, D=t1/t2 3. TJM - TC = PDM * Zθ JC(t) single pulse 0.1 1E-5 1E-4 1E-3 0.01 0.1 1 10 100 1000 t1, Square Wave Pulse Duration [sec] Thermal Response 9 FSDL0365RN, FSDM0365RN Typical Performance Characteristics (Control Part) (These characteristic graphs are normalized at Ta = 25°C) 1.20 1.00 Normalized 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ℃] 100 150 Normalized 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ℃] 100 150 Operating Frequency (Fosc) Frequency Modulation (FMOD) 1.20 1.00 Normalized 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ℃] 100 150 Normalized 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ℃] 100 150 Maximum duty cycle (Dmax) Operating supply current (Iop) 1.20 1.00 Normalized 1.20 1.00 0.80 0.60 0.40 0.20 0.00 Nomalized 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ℃] 100 150 -50 0 50 T emp[ ℃] 100 150 Start Threshold Voltage (Vstart) Stop Threshold Voltage (Vstop) 10 FSDL0365RN, FSDM0365RN Typical Performance Characteristics (Continued) 1.20 1.00 Normalized Normalized 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ℃] 100 150 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ℃] 100 150 Feedback Source Current (Ifb) Peak current limit (Iover) 1.20 1.00 Normalized 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ℃] 100 150 Normalized 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ℃] 100 150 Start up Current (Istart) J-FET Start up current (Istr) 1.20 1.00 Normalized 1.20 1.00 Normalized 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ℃] 100 150 0.80 0.60 0.40 0.20 0.00 -50 0 50 Temp[℃] 100 150 Burst peak current (Iburst) Over Voltage Protection (Vovp) 11 FSDL0365RN, FSDM0365RN Functional Description 1. Startup : In previous generations of Fairchild Power Switches (FPS) the Vstr pin had an external resistor to the DC input voltage line. In this generation the startup resistor is replaced by an internal high voltage current source and a switch that shuts off when 15mS goes by after the supply voltage, Vcc, gets above 12V. The source turns back on if Vcc drops below 8V. Vcc 2uA Vref 0.9mA Vo Vfb FB 3 Cfb OSC D1 D2 28R Vfb* R Gate driver 431 Vin,dc Istr VSD OLP Figure 5. Pulse width modulation (PWM) circuit Vstr Vcc UVLO 12V) off J-FET Figure 4. High voltage current source 2. Feedback Control : The FSDx0365RN employs current mode control, shown in figure 5. An opto-coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. When the reference pin voltage of the KA431 exceeds the internal reference voltage of 2.5V, the H11A817A LED current increases, thus pulling down the feedback voltage and reducing the duty cycle. This event typically happens when the input voltage is increased or the output load is decreased. 4. Protection Circuit : The FPS has several protective functions such as over load protection (OLP), over voltage protection (OVP), abnormal over current protection (AOCP), under voltage lock out (UVLO) and thermal shutdown (TSD). Because these protection circuits are fully integrated inside the IC without external components, the reliability is improved without increasing cost. Once the fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage, 8V, the protection is reset and the internal high voltage current source charges the Vcc capacitor via the Vstr pin. When Vcc reaches the UVLO start voltage,12V, the FPS resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated. 3. Leading edge blanking (LEB) : At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by the primary side capacitance and secondary side rectifier diode reverse recovery. Excessive voltage across the Rsense resistor would lead to incorrect feedback operation in the current mode PWM control. To counter this effect, the FPS employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (TLEB) after the Sense FET is turned on. 4.1 Over Load Protection (OLP) : Overload is defined as the load current exceeding a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated in order to protect the SMPS. However, even when the SMPS is in the normal operation, the over load protection circuit can be activated during the load transition. In order to avoid this undesired operation, the over load protection circuit is designed to be activated after a specified time to determine whether it is a transient situation or an overload situation. In conjunction with the Ipk current limit pin (if used) the current mode feedback path would limit the current in the Sense FET when the maximum PWM duty cycle is attained. If the output consumes more than this maximum power, the output voltage (Vo) decreases below the set voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (Vfb). If Vfb exceeds 3V, the feedback input diode is blocked and the 5uA Idelay current source starts to charge Cfb slowly up to Vcc. In this condition, Vfb continues increasing until it reaches 6V, when the switching operation is terminated as shown in figure 6. The delay time for shutdown is the time required to charge Cfb from 3V to 6V with 5uA. 12 FSDL0365RN, FSDM0365RN Vcc 8V OLP 6V monitors the current through the sensing resistor. The voltage across the resistor is then compared with a preset AOCP level. If the sensing resistor voltage is greater than the AOCP level, pulse by pulse AOCP is triggered regardless of uncontrollable LEB time. Here, pulse by pulse AOCP stops Sense FET within 350nS after it is activated. FPS switching Following Vcc 3V Delay current (5uA) charges the Cfb t1 t1 = − 1 RC t2 In (1 − fb t3 t4 t V ( t 1) ); V ( t1) = 3V , R = 2 . 8 K Ω , C fb = C R fb _ fig . 2 t 2 = C fb (V (t1 + t 2) − V (t1)) ; I delay = 5uA,V (t1 + t 2) − V (t1) = 3V I delay Figure 6. Over load protection 4.2 Thermal Shutdown (TSD) : The Sense FET and the control IC are integrated, making it easier for the control IC to detect the temperature of the Sense FET. When the temperature exceeds approximately 140°C, thermal shutdown is activated. 4.4 Over Voltage Protection (OVP) : In case of malfunction in the secondary side feedback circuit, or feedback loop open caused by a defect of solder, the current through the opto-coupler transistor becomes almost zero. Then, Vfb climbs up in a similar manner to the over load situation, forcing the preset maximum current to be supplied to the SMPS until the over load protection is activated. Because excess energy is provided to the output, the output voltage may exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an over voltage protection (OVP) circuit is employed. In general, Vcc is proportional to the output voltage and the FPS uses Vcc instead of directly monitoring the output voltage. If VCC exceeds 19V, OVP circuit is activated resulting in termination of the switching operation. In order to avoid undesired activation of OVP during normal operation, Vcc should be properly designed to be below 19V. 4.3 Abnormal Over Current Protection (AOCP) : PW M COM PARATOR Vfb LEB CLK Out Driver Drain Vsense AOCP COMPARATOR S R Q 5. Soft Start : The FPS has an internal soft start circuit that increases the feedback voltage together with the Sense FET current slowly after it starts up. The typical soft start time is 15msec, as shown in figure 8, where progressive increments of Sense FET current are allowed during the start-up phase. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce the stress on the secondary diode. VAOCP Rsense Drain current [A] Figure 7. AOCP Function & Block 2.15A 1mS 15steps Even though the FPS has OLP (Over Load Protection) and current mode PWM feedback, these are not enough to protect the FPS when a secondary side diode short or a transformer pin short occurs. In addition to start-up, soft-start is also activated at each restart attempt during auto-restart and when restarting after latch mode is activated. The FPS has an internal AOCP (Abnormal Over Current Protection) circuit as shown in figure 7. When the gate turn-on signal is applied to the power Sense FET, the AOCP block is enabled and Current limit 0.98A t 13 FSDL0365RN, FSDM0365RN 5V D R A IN Burst Operation Feedback Burst Operation Normal Operation S W IT C H OFF GND 0.5V 0.3V Current waveform Switching OFF Switching OFF I_ o v e r Rsense Figure 8. Soft Start Function Figure 10. Circuit for Burst Operation 6. Burst operation :In order to minimize power dissipation in standby mode, the FPS enters burst mode operation. 7. Frequency Modulation : EMI reduction can be accomplished by modulating the switching frequency of a switched power supply. Frequency modulation can reduce EMI by spreading the energy over a wider frequency range than the band width measured by the EMI test equipment. The amount of EMI reduction is directly related to the depth of the reference frequency. As can be seen in Figure 11, the frequency changes from 65KHz to 69KHz in 4mS for the FSDM0265RN. Frequency modulation allows the use of a cost effective inductor instead of an AC input mode choke to satisfy the requirements of world wide EMI limits. + 0.3/0.5V 0.5V Vcc IB_PEAK Vcc Idelay Vcc IFB FB 3 Normal PWM Burst 2.5R R MOSFET Current Internal O scillator Figure 9. Circuit for Burst operation 69kH z As the load decreases, the feedback voltage decreases. As shown in figure 10, the device automatically enters burst mode when the feedback voltage drops below VBURH(500mV). Switching still continues but the current limit is set to a fixed limit internally to minimize flux density in the transformer. The fixed current limit is larger than that defined by Vfb = VBURH and therefore, Vfb is driven down further. Switching continues until the feedback voltage drops below VBURL(300mV). At this point switching D rain to S ourc e voltage D rain to S ource current V ds W aveform 65kH z 67kH z 69kH z T urn-on T urn-off point 4k H z stops and the output voltages start to drop at a rate dependent on the standby current load. This causes the feedback voltage to rise. Once it passes VBURH(500mV) switching resumes. The feedback voltage then falls and the process repeats. Burst mode operation alternately enables and disables switching of the power Sense FET thereby reducing switching loss in Standby mode. Figure 11. Frequency Modulation Waveform 14 FSDL0365RN, FSDM0365RN 5uA 900uA Amplitude (dBµV) CISPR2QB CISPR2AB Feed Back 3 2 KΩ Current Limit PWM comparator 4 AK Ω 0.8 KΩ Rsense SenseFET Sense Figure 14. Peak current adjustment Frequency (MHz) Figure 12. KA5-series FPS Full Range EMI scan(67KHz, no Frequency Modulation) with DVD Player SET For example, FSDx0265RN has a typical Sense FET current limit (IOVER) of 2.15A. The Sense FET current can be limited to 1A by inserting a 2.8kΩ between the current limit pin and ground which is derived from the following equations: 2.15: 1 = 2.8KΩ : XKΩ , CISPR2QB Amplitude (dBµV) CISPR2AB X = 1.3KΩ, Since X represents the resistance of the parallel network, Y can be calculated using the following equation: Y = X / (1 - (X/2.8KΩ)) Frequency (MHz) Figure 13. FSDX-series FPS Full Range EMI Scan (67KHz, with Frequency Modulation) with DVD Player SET 8. Adjusting Current limit function: As shown in fig 14, a combined 2.8KΩ internal resistance is connected into the non-inverting lead on the PWM comparator. A external resistance of Y on the current limit pin forms a parallel resistance with the 2.8KΩ when the internal diodes are biased by the main current source of 900uA. 15 FSDL0365RN, FSDM0365RN Typical application circuit 1. Set Top Box Example Circuit (20W Output Power) 2A/250V FUSE 12 C7 400V /47u R3 56K/1/ 4W LF1 40mH KBP06M 100pF /400V C2 5 D start R1 47K C8 6.8n/ 1kV D5 UF4007 1 D12 R15 EGP20D 20R C17 100uF /50V L3 C15 470uF /35V L2 C14 470uF /10V +5.0V 0.2~0.85A R20 100uF /50V +17.0V D13 EGP20D C16 220uF /35V 0.01~0.5A +23.0V 0.005~0.45A 85VAC ~275VAC 100pF /400V C1 11 3 GreenFPS PERFORMANCE SUMMARY Output Power: 20W Regulation 3.3V: ±5% 5.0V: ±5% 17.0V: ±7% 23.0: ±7% Efficiency: ≥75% No load Consumption: 0.12W at 230Vac D D 10 D14 EGP20D FSDM0365RN S VccVfb I_pk 1 R5 6kR C6 50V 47uF R4 30R D6 UF4004 5 C9 33n 50V PC817 Q1 FOD2741A PC817 SB360 D15 C13 1000uF /16V L1 4 6 8 R21 330R C11 1000uF /16V R14 R22 1KR 800R 0.1uF/ monolithic C209 R15 6.9K TL431AZ C12 470uF /10V R13 2.7K R19 +3.3V 0.4~1.4A R12 1.5K Figure15. 20W multiple power supply using FSDM0365RN Multiple Output, 20W, 85-265VAC Input Power supply: Figure 15 shows a multiple output supply typical for high end set-top boxes containing high capacity hard disks for recording or LIPS(LCD Inverter Power Supply) for 15" LCD monitor. The supply delivers an output power of 20W cont./24 W peak (thermally limited) from an input voltage of 85 to 265 VAC. Efficiency at 20W, 85VAC is ≥75%. The 3.3 V and 5 V outputs are regulated to ±5% without the need for secondary linear regulators. DC stacking (the secondary winding reference for the other output voltages is connected to the anode of D15. For more accuracy, connection to the cathode of D15 will be better.) is used to minimize the voltage error for the higher voltage outputs. Due to the high ambient operating temperature requirement typical of a set-top box (60 °C) the FSDL0165RN is used to reduce conduction losses without a heatsink. Resistor R5 sets the device current limit to limit overload power. Leakage inductance clamping is provided by R1 and C8, keeping the DRAIN voltage below 650 V under all conditions. Resistor R1 and capacitor C8 are selected such that R1 dissipates power to prevent rising of DRAIN Voltage caused by leakage inductance. The frequency modulation feature of FSDL0165RN allows the circuit shown to meet CISPR2AB with simple EMI filtering (C1, LF1 and C2) and the output grounded. The secondaries are rectified and smoothed by D12, D13, D14,and D15. Diode D15 for the 3.4V output is a Schottky diode to maximize efficiency. Diode D14 for the 5 V output is a PN type to center the 5 V output at 5 V. The 3.3 V and 5 V output voltage require two capacitors in parallel to meet the ripple current requirement. Switching noise filter- ing is provided by L3, L2 and L1. Resistor R15 prevents peak charging of the lightly loaded 23V output. The outputs are regulated by the reference (TL431) voltage in secondary. Both the 3.3 V and 5 V outputs are sensed via R13 and R14. Resistor R22 provides bias for TL431and R21 sets the overall DC gain. Resistor R21, C209, R14 and R13 provide loop compensation. 16 FSDL0365RN, FSDM0365RN 2. Transformer Specification 1. - TR AN SFO RM ER SPECIFICATIO N SCHEM ATIC DIAG R AM (TR ANSFO RM ER) 3mm 1 2 3 4 5 12 11 10 8 7 6 W INDING SPEC IFIC ATIO N top 6mm NB N P/2 N 23V N 17V N 5V N 3.3V N P/2 bottom 2. N O. N P/2 N 3.3V N 5V N 16V N 23V N P/2 NB P IN(S → F ) 3→2 6 →8 W IRE 0 .25 Φ × 1 0 .3 Φ × 8 0 .3 Φ × 2 0 .3 Φ × 4 0.3 Φ × 2 0 .25 Φ × 1 0 .25 Φ × 1 T URNS 22 2 1 7 3 22 10 W INDING METHOD SOLENOID W INDING S TACK W INDING S TACK W INDING S OLENOID W INDING S OLENOID W INDING SOLENOID W INDING CENTER W INDING 10 → 6 11 → 6 12 → 11 2→1 4→5 3. ELECTRIC CH AR ACTERISTIC C LOSURE INDUCTANCE L EAKAGE L P IN 1-3 1-3 S PEC. 800uH ± 10% 15uH MAX. R EM ARKS 1KHz, 1V 2nd ALL SHORT 4 . BOBBIN & CO R E. C ORE: BO BBIN: EER 2828 EER 2828 17 FSDL0365RN, FSDM0365RN Layout Considerations SURFACE MOUNTED COPPER AREA FOR HEAT SINKING DC_link Capacitor #1 : GND #2 : VCC #3 : Vfb #4 : Ipk #5 : Vstr #6 : Drain #7 : Drain #8 : Drain Y1CAPACITOR -+ DC OUT Figure 15. Layout Considerations for FSDx0365RN using 8DIP 18 FSDL0365RN, FSDM0365RN Package Dimensions 8DIP 19 FSDL0365RN, FSDM0365RN Package Dimensions (Continued) 8LSOP 20 FSDL0365RN, FSDM0365RN Ordering Information Product Number FSDM0365RN FSDL0365RN FSDM0365RL FSDL0365RL Package 8DIP 8DIP 8LSOP 8LSOP Marking Code DM0365R DL0365R DM0365R DL0365R BVDSS 650V 650V 650V 650V FOSC 67KHz 50KHz 67KHz 50KHz RDS(on) 3.6Ω 3.6Ω 3.6Ω 3.6Ω 21 FSDL0365RN, FSDM0365RN DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 6/17/04 0.0m 001  2004 Fairchild Semiconductor Corporation 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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