FSDL0165RL

www.fairchildsemi.com FSDH321, FSDL321 Features • Internal Avalanche Rugged Sense FET • Consumes only 0.65W at 240VAC & 0.3W load with Advanced Burst-Mode Operation • Frequency Modulation for EMI Reduction • Precision Fixed Operating Frequency • Internal Start-up Circuit • Pulse-by-Pulse Current Limiting • Abnormal Over Current Protection (AOCP) • Over Voltage Protection (OVP) • Over Load Protection (OLP) • Internal Thermal Shutdown Function (TSD) • Auto-Restart Mode • Under Voltage Lockout (UVLO) • Low Operating Current (max 3mA) • Adjustable Peak Current Limit • Built-in Soft Start Green Mode Fairchild Power Switch (FPSTM) OUTPUT POWER TABLE 230VAC ±15%(3) PRODUCT FSDL321 FSDH321 FSDL0165RN FSDM0265RN FSDH0265RN FSDL0365RN FSDM0365RN FSDL321L FSDH321L FSDL0165RL FSDM0265RL FSDH0265RL FSDL0365RL FSDM0365RL Adapter(1) 11W 11W 13W 16W 16W 19W 19W 11W 11W 13W 16W 16W 19W 19W Open Frame(2) 17W 17W 23W 27W 27W 30W 30W 17W 17W 23W 27W 27W 30W 30W 85-265VAC Adapter(1) 8W 8W 11W 13W 13W 16W 16W 8W 8W 11W 13W 13W 16W 16W Open Frame(2) 12W 12W 17W 20W 20W 24W 24W 12W 12W 17W 20W 20W 24W 24W Applications • SMPS for STB, Low cost DVD Player • Auxiliary Power for PC • Adapter & Charger Related Application Notes • AN-4137, 4141, 4147(Flyback) / AN-4134(Forward) Description Each product in the FSDx321 (x for H, L) family consists of an integrated Pulse Width Modulator (PWM) and Sense FET, and is specifically designed for high performance offline Switch Mode Power Supplies (SMPS) with minimal external components. Both devices are integrated high voltage power switching regulators which combine an avalanche rugged Sense FET with a current mode PWM control block. The integrated PWM controller features include: a fixed oscillator with frequency modulation for reduced EMI, Under Voltage Lock Out (UVLO) protection, Leading Edge Blanking (LEB), an optimized gate turn-on/turn-off driver, Thermal Shut Down (TSD) protection, Abnormal Over Current Protection (AOCP) and temperature compensated precision current sources for loop compensation and fault protection circuitry. When compared to a discrete MOSFET and controller or RCC switching converter solution, the FSDx321 devices reduce total component count, design size, weight while increasing efficiency, productivity and system reliability. Both devices provide a basic platform that is well suited for the design of cost-effective flyback converters. FPSTM is a trademark of Fairchild Semiconductor Corporation. ©2005 Fairchild Semiconductor Corporation Notes: 1. Typical continuous power in a non-ventilated enclosed adapter with sufficient drain pattern as a heat sinker, at 50°C ambient. 2. Maximum practical continuous power in an open frame design with sufficient drain pattern as a heat sinker, at 50°C ambient. 3. 230 VAC or 100/115 VAC with doubler. Typical Circuit AC IN DC OUT Vstr Ipk PWM Vfb Drain Vcc Source Figure 1. Typical Flyback Application Rev.1.0.5 FSDH321, FSDL321 Internal Block Diagram Vcc 2 + Vstr 5 Drain 6,7,8 ICH 8V/12V Vcc V BURH - Vcc good Freq. Modulation OSC Vref V BURL /V BURH IBUR(pk) Vcc IDELAY Vcc I FB Internal Bias Vfb 3 Normal PWM Burst S R Q Q 2.5R Ipk 4 Soft Start R Gate driver LEB V SD Vcc Vovp Vcc good TSD R Q 1 GND S Q AOCP Vocp Figure 2. Functional Block Diagram of FSDx321 2 FSDH321, FSDL321 Pin Definitions Pin Number 1 Pin Name GND Pin Function Description Sense FET source terminal on primary side and internal control ground. Positive supply voltage input. Although connected to an auxiliary transformer winding, current is supplied from pin 5 (Vstr) via an internal switch during startup (see Internal Block Diagram section). It is not until Vcc reaches the UVLO upper threshold (12V) that the internal start-up switch opens and device power is supplied via the auxiliary transformer winding. The feedback voltage pin is the non-inverting input to the PWM comparator. It has a 0.9mA current source connected internally while a capacitor and optocoupler are typically connected externally. A feedback voltage of 6V triggers over load protection (OLP). There is a time delay while charging external capacitor Cfb from 3V to 6V using an internal 5uA current source. This time delay prevents false triggering under transient conditions, but still allows the protection mechanism to operate under true overload conditions. This pin adjusts the peak current limit of the Sense FET. The feedback 0.9mA current source is diverted to the parallel combination of an internal 2.8kΩ resistor and any external resistor to GND on this pin to determine the peak current limit. If this pin is tied to Vcc or left floating, the typical peak current limit will be 0.7A. This pin connects directly to the rectified AC line voltage source. At start up the internal switch supplies internal bias and charges an external storage capacitor placed between the Vcc pin and ground. Once the Vcc reaches 12V, the internal switch is opened. The drain pins are designed to connect directly to the primary lead of the transformer and are capable of switching a maximum of 650V. Minimizing the length of the trace connecting these pins to the transformer will decrease leakage inductance. 2 Vcc 3 Vfb 4 Ipk 5 Vstr 6, 7, 8 Drain Pin Configuration 8DIP 8LSOP GND 1 Vcc 2 Vfb 3 Ipk 4 8 Drain 7 Drain 6 Drain 5 Vstr Figure 3. Pin Configuration (Top View) 3 FSDH321, FSDL321 Absolute Maximum Ratings (Ta=25°C, unless otherwise specified) Characteristic Drain Pin Voltage Vstr Pin Voltage Drain-Gate Voltage Gate-Source Voltage Drain Current Pulsed(1) Continuous Drain Current (Tc=25℃) Continuous Drain Current (Tc=100℃) Single Pulsed Avalanche Energy Supply Voltage Feedback Voltage Range Total Power Dissipation Operating Junction Temperature Operating Ambient Temperature Storage Temperature (2) Symbol VDRAIN VSTR VDG VGS IDM ID ID EAS VCC VFB PD TJ TA TSTG Value 650 650 650 ± 20 1.5 0.7 0.32 10 20 -0.3 to VCC 1.40 Internally limited -25 to +85 -55 to +150 Unit V V V V A A A mJ V V W °C °C °C Note: 1. Repetitive rating: Pulse width is limited by maximum junction temperature 2. L = 24mH, starting Tj = 25°C Thermal Impedance (Ta=25°C, unless otherwise specified) Parameter 8DIP Junction-to-Ambient Thermal(1) Junction-to-Case Thermal(2) Symbol Value 88.84 13.94 Unit °C/W °C/W θJA θJC Note: 1. Free standing with no heatsink; Without copper clad. / Measurement Condition : Just before junction temperature TJ enters into OTP. 2. Measured on the DRAIN pin close to plastic interface. - all items are tested with the standards JESD 51-2 and 51-10 (DIP). 4 FSDH321, FSDL321 Electrical Characteristics (Ta = 25°C unless otherwise specified) Parameter SENSE FET SECTION Zero-Gate-Voltage Drain Current Drain-Source On-State Resistance Forward Trans-Conductance(1) Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain (Miller) Charge CONTROL SECTION Switching Frequency Switching Frequency Modulation Switching Frequency Switching Frequency Modulation Switching Frequency Variation(2) Maximum Duty Cycle UVLO Threshold Voltage Feedback Source Current Internal Soft Start Time BURST MODE SECTION Burst Mode Voltage PROTECTION SECTION Peak Current Limit Current Limit Delay Time(3) Thermal Shutdown Temperature(3) Shutdown Feedback Voltage Over Voltage Protection Shutdown Delay Current Leading Edge Blanking Time TOTAL DEVICE SECTION Operating Supply Current (control part only) Start-Up Charging Current Vstr Supply Voltage Symbol IDSS RDS(ON) gfs CISS COSS CRSS td(on) tr td(off) tf Qg Qgs Qgd fOSC ∆fMOD fOSC ∆fMOD ∆fOSC DMAX VSTART VSTOP IFB tS/S VBURH VBURL Condition VDS=650V, VGS=0V VDS=520V, VGS=0V, TC=125°C VGS=10V, ID=0.5A VDS=50V, ID=0.5A VGS=0V, VDS=25V, f=1MHz Min. 1.0 90 ±2.5 45 ±1.0 62 71 11 7 0.7 10 0.4 0.25 Typ. 14 1.3 162 18 3.8 9.5 19 33 42 7.0 3.1 0.4 100 ±3.0 50 ±1.5 ±5 67 77 12 8 0.9 15 0.5 0.35 150 0.70 600 145 6.0 19 5.0 3 0.85 Max. 25 200 19 110 ±3.5 55 ±2.0 ±10 72 83 13 9 1.1 20 0.6 0.45 0.80 6.5 20 6.5 5 1.0 Unit µA Ω S pF VDS=325V, ID=1.0A ns VGS=10V, ID=1.0A, VDS=325V nC FSDH321 FSDL321 -25°C ≤ Ta ≤ 85°C FSDH321 FSDL321 VFB=GND VFB=GND VFB=GND VFB=4V Tj=25°C KHz KHz KHz KHz % % % V V mA ms V V mV A ns °C V V µA ns mA mA V VBUR(HYS) Hysteresis ILIM tCLD TSD VSD VOVP IDELAY tLEB IOP ICH VSTR Tj=25°C, ∆i/∆t=250mA/us 0.60 Tj=25°C 125 5.5 18 VFB=4V 3.5 200 VCC=14V, VFB=0V VCC=0V VCC=0V 1 0.7 35 Note: 1. Pulse test: Pulse width ≤ 300us, duty ≤ 2% 2. These parameters, although guaranteed, are tested in EDS (wafer test) process 3. These parameters, although guaranteed, are not 100% tested in production 5 FSDH321, FSDL321 Comparison Between FSDM311 and FSDx321 Function Soft-Start FSDM311 15ms 15ms FSDx321 FSDx321 Advantages (same for both devices) • Gradually increasing current limit during soft-start further reduces peak current and voltage stresses • Eliminates external components used for soft-start in most applications • Reduces or eliminates output overshoot • Smaller transformer • Allows power limiting (constant overload power) • Allows use of larger device for lower losses and higher efficiency. • Reduces conducted EMI (same for both devices) • Improves light load efficiency • Reduces power consumption at noload • Transformer audible noise reduction (same for both devices) • Greater immunity to arcing provoked by dust, debris and other contaminants External Current Limit not applicable Programmable of default current limit Frequency Modulation Burst Mode Operation not applicable Built into controller ±3.0KHz @100KHz ±1.5KHz @50KHz Built into controller Drain Creepage at Package 7.62mm 7.62mm 6 FSDH321, FSDL321 Typical Performance Characteristics (Control Part) (These characteristic graphs are normalized at Ta = 25°C) 1.20 1.00 Normalized 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ℃] 100 150 Normalized 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[℃] 100 150 Operating Frequency (Fosc) vs. Ta Frequency Modulation (∆FMOD) vs. Ta 1.20 1.00 Normalized 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[℃] 100 150 Normalized 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ℃] 100 150 Maximum Duty Cycle (DMAX) vs. Ta Operating Supply Current (IOP) vs. Ta 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[℃] 100 150 1.20 1.00 Normalized 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[℃] 100 150 Normalized Start Threshold Voltage (VSTART) vs. Ta Stop Threshold Voltage (VSTOP) vs. Ta 7 FSDH321, FSDL321 Typical Performance Characteristics (Continued) 1.20 1.00 Normalized Normalized 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[℃] 100 150 -50 0 50 T emp[℃] 100 150 0.80 0.60 0.40 0.20 0.00 Feedback Source Current (IFB) vs. Ta Start Up Charging Current (ICH) vs. Ta 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[℃] 100 150 1.20 1.00 Normalized 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[ ℃] 100 150 Normalized Peak Current Limit (ILIM) vs. Ta Burst Peak Current (IBUR(pk)) vs. Ta 1.20 1.00 Normalized 0.80 0.60 0.40 0.20 0.00 -50 0 50 T emp[℃] 100 150 Over Voltage Protection (VOVP) vs. Ta 8 FSDH321, FSDL321 Functional Description 1. Startup : In previous generations of Fairchild Power Switches (FPSTM) the Vstr pin had an external resistor to the DC input voltage line. In this generation the startup resistor is replaced by an internal high voltage current source and a switch that shuts off when 15ms goes by after the supply voltage, Vcc, gets above 12V. The source turns back on if Vcc drops below 8V. 3. Leading Edge Blanking (LEB) : At the instant the internal Sense FET is turned on, the primary side capacitance and secondary side rectifier diode reverse recovery typically cause a high current spike through the Sense FET. Excessive voltage across the Rsense resistor leads to incorrect feedback operation in the current mode PWM control. To counter this effect, the FPS employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (tLEB) after the Sense FET is turned on. Vin,dc ISTR Vstr Vcc Vcc70% at full load, full input range) Low standby mode power consumption (