FSDM07652RB

www.fairchildsemi.com FSDM0565RB Features Green Mode Fairchild Power Switch (FPSTM) • Internal Avalanche Rugged Sense FET • Advanced Burst-Mode operation consumes under 1 W at 240VAC & 0.5W load • Precision Fixed Operating Frequency (66kHz) • Internal Start-up Circuit • Improved Pulse by Pulse Current Limiting • Over Voltage Protection (OVP) • Over Load Protection (OLP) • Internal Thermal Shutdown Function (TSD) • Auto-Restart Mode • Under Voltage Lock Out (UVLO) with hysteresis • Low Operating Current (2.5mA) • Built-in Soft Start OUTPUT POWER TABLE 230VAC ±15%(3) PRODUCT FSDM0565RB FSDM0565RBI FSDM07652RB Adapter(1) 60W 60W 70W Open Frame(2) 70W 70W 80W 85-265VAC Adapter(1) 50W 50W 60W Open Frame(2) 60W 60W 70W Table 1. Maximum Output Power Notes: 1. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient. 2. Maximum practical continuous power in an open frame design at 50°C ambient. 3. 230 VAC or 100/115 VAC with doubler. Application • SMPS for LCD monitor and STB • Adaptor Description The FSDM0565RB is an integrated Pulse Width Modulator (PWM) and Sense FET specifically designed for high performance offline Switch Mode Power Supplies (SMPS) with minimal external components. This device is an integrated high voltage power switching regulator which combine an avalanche rugged Sense FET with a current mode PWM control block. The PWM controller includes integrated fixed frequency oscillator, under voltage lockout, leading edge blanking (LEB), optimized gate driver, internal soft start, temperature compensated precise current sources for a loop compensation and self protection circuitry. Compared with discrete MOSFET and PWM controller solution, it can reduce total cost, component count, size and weight simultaneously increasing efficiency, productivity, and system reliability. This device is a basic platform well suited for cost effective designs of flyback converters. Typical Circuit AC IN DC OUT Vstr PWM Vfb Drain Vcc Source Figure 1. Typical Flyback Application FPSTM is a trademark of Fairchild Semiconductor Corporation. ©2006 Fairchild Semiconductor Corporation Rev.1.0.6 FSDM0565RB Internal Block Diagram Vcc 3 N.C 5 0.5/0.7V + Vstr 6 Drain 1 Istart Vref 8V/12V Vcc good Internal Bias Vcc Idelay Vref OSC IFB 2.5R PWM S Q FB 4 R Q Soft start R Gate driver LEB VSD Vcc S Q 2 GND Vovp TSD Vcc good R Q VCL Figure 2. Functional Block Diagram of FSDM0565RB 2 FSDM0565RB Pin Definitions Pin Number 1 2 3 Pin Name Drain GND Vcc Pin Function Description This pin is the high voltage power Sense FET drain. It is designed to drive the transformer directly. This pin is the control ground and the Sense FET source. This pin is the positive supply voltage input. During start up, the power is supplied by an internal high voltage current source that is connected to the Vstr pin. When Vcc reaches 12V, the internal high voltage current source is disabled and the power is supplied from the auxiliary transformer winding. This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 6.0V, the over load protection is activated resulting in shutdown of the FPSTM. This pin is connected directly to the high voltage DC link. At startup, the internal high voltage current source supplies internal bias and charges the external capacitor that is connected to the Vcc pin. Once Vcc reaches 12V, the internal current source is disabled. 4 Vfb 5 6 N.C Vstr Pin Configuration TO-220F-6L 6.Vstr 5.N.C. 4.Vfb 3.Vcc 2.GND 1.Drain I2-PAK-6L 6.Vstr 5.N.C. 4.Vfb 3.Vcc 2.GND 1.Drain Figure 3. Pin Configuration (Top View) 3 FSDM0565RB Absolute Maximum Ratings (Ta=25°C, unless otherwise specified) Parameter Drain-source voltage Vstr Max Voltage Pulsed Drain current (Tc=25°C) (1) Symbol VDSS VSTR IDM ID EAS IAS VCC VFB Value 650 650 11 2.8 1.7 190 20 -0.3 to VCC 45 (TO-220-6L) 75 (I2-PAK-6L) Internally limited -25 to +85 -55 to +150 2.0 (GND-Vstr/Vfb=1.5kV) 300 (GND-Vstr/Vfb=225V) Unit V V ADC A A mJ A V V Continuous Drain Current(Tc=25°C) Continuous Drain Current(Tc=100°C) Single pulsed avalanche energy Single pulsed avalanche current Supply voltage Input voltage range Total power dissipation(Tc=25°C) (2) (3) PD(Watt H/S) W °C °C °C kV V Operating junction temperature Operating ambient temperature Storage temperature range ESD Capability, HBM Model (All pins excepts for Vstr and Vfb) ESD Capability, Machine Model (All pins excepts for Vstr and Vfb) Tj TA TSTG - Notes: 1. Repetitive rating: Pulse width limited by maximum junction temperature 2. L=14mH, starting Tj=25°C 3. L=13uH, starting Tj=25°C Thermal Impedance Parameter Junction-to-Ambient Thermal Junction-to-Case Thermal Symbol Package TO-220F-6L I2-PAK-6L TO-220F-6L I2-PAK-6L Value 49.90 30 2.78 1.67 Unit °C/W °C/W θJA(1) θJC(2) Notes: 1. Free standing with no heat-sink under natural convection. 2. Infinite cooling condition - Refer to the SEMI G30-88. 4 FSDM0565RB Electrical Characteristics (Ta = 25°C unless otherwise specified) Parameter Sense FET SECTION Drain source breakdown voltage BVDSS VGS = 0V, ID = 250μA VDS = 650V, VGS = 0V Zero gate voltage drain current Static drain source on resistance (1) Output capacitance Turn on delay time Rise time Turn off delay time Fall time CONTROL SECTION Initial frequency Voltage stability Temperature stability (2) Maximum duty cycle Minimum duty cycle Start threshold voltage Stop threshold voltage Feedback source current Soft-start time Leading Edge Blanking time BURST MODE SECTION Burst Mode Voltages (2) PROTECTION SECTION Peak current limit (4) Over voltage protection Thermal shutdown temperature (2) Shutdown feedback voltage Shutdown delay current IOVER VOVP TSD VSD IDELAY VFB ≥ 5.5V VFB=5V VFB=5V, VCC=14V 2.0 18 130 5.5 2.8 2.25 19 145 6.0 3.5 2.5 20 160 6.5 4.2 A V °C V μA VBURH VBURL Vcc=14V Vcc=14V 0.7 0.5 V V FOSC FSTABLE ΔFOSC DMAX DMIN VSTART VSTOP IFB TS TLEB VFB=GND VFB=GND VFB=GND Vfb=3 VFB = 3V 13V ≤ Vcc ≤ 18V -25°C ≤ Ta ≤ 85°C 60 0 0 77 11 7 0.7 66 1 ±5 82 12 8 0.9 10 250 72 3 ±10 87 0 13 9 1.1 15 kHz % % % % V V mA ms ns IDSS VDS= 520V VGS = 0V, TC = 125°C VGS = 10V, ID = 2.5A VGS = 0V, VDS = 25V, f = 1MHz VDD= 325V, ID= 5A (MOSFET switching time is essentially independent of operating temperature) 650 1.76 78 22 52 95 50 500 500 2.2 ns V μA μA Ω Symbol Condition Min. Typ. Max. Unit RDS(ON) COSS TD(ON) TR TD(OFF) TF pF 5 FSDM0565RB TOTAL DEVICE SECTION IOP Operating supply current (5) VFB=GND, VCC=14V VFB=GND, VCC=10V VFB=GND, VCC=18V 2.5 5 mA IOP(MIN) IOP(MAX) Notes: 1. Pulse test : Pulse width ≤ 300μS, duty ≤ 2% 2. These parameters, although guaranteed at the design, are not tested in mass production. 3. These parameters, although guaranteed, are tested in EDS(wafer test) process. 4. These parameters indicate the inductor current. 5. This parameter is the current flowing into the control IC. 6 FSDM0565RB Comparison Between FS6M07652RTC and FSDM0565RB Function Soft-Start FS6M07652RTC Adjustable soft-start time using an external capacitor FSDM0565RB FSDM0565RB Advantages Internal soft-start with • Gradually increasing current limit typically 10ms (fixed) during soft-start further reduces peak current and voltage component stresses • Eliminates external components used for soft-start in most applications • Reduces or eliminates output overshoot Burst Mode Operation • Built into controller • Built into controller • Improve light load efficiency • Output voltage fixed • Reduces no-load consumption • Output voltage drops to around half 7 FSDM0565RB Typical Performance Characteristics (These Characteristic Graphs are Normalized at Ta= 25°C) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 150 Ju nc tion Te mpe ratu re (℃) 1.2 1.0 Start Thershold Voltage (Vstart) 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 150 Ju nc tion Te mpe ratu re (℃) Operating Current (Iop) Operating Current vs. Temp 1.2 1.0 Stop Threshold Voltage (Vstop) Operating Frequency (Fosc) Start Threshold Voltage vs. Temp 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 150 Ju nc tion Te mpe ratu re (℃) -25 0 25 50 75 100 125 150 Ju nc tion Te mpe ratu re (℃) Stop Threshold Voltage vs. Temp Operating Freqency vs. Temp 1.2 1.0 Maximum Duty Cycle (Dmax) 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 150 Ju nc tion Te mpe ratu re (℃) 1.2 1.0 FB Source Current (Ifb) 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 150 Ju nction Te mperatu re(℃) Maximum Duty vs. Temp Feedback Source Current vs. Temp 8 FSDM0565RB Typical Performance Characteristics (Continued) (These Characteristic Graphs are Normalized at Ta= 25°C) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 150 Ju n c tion Te mpe ratu re (℃) 1.2 1.0 Shutdown Delay Current (Idelay) 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 150 Ju n c tion T e mpe ra tu re (℃) Shutdown FB Voltage (Vsd) ShutDown Feedback Voltage vs. Temp ShutDown Delay Current vs. Temp 1.2 Over Voltage Protection (Vovp) 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 150 Junction Temperature(℃) FB Burst Mode Enable Voltage (Vfbe) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Over Voltage Protection vs. Temp Burst Mode Enable Voltage vs. Temp 1.2 Peak Current Limit(Self protection) (Iover) 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 125 Ju n c tion Te mpe ratu re (℃) FB Burst Mode Disable Voltage (Vfbd) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Burst Mode Disable Voltage vs. Temp Current Limit vs. Temp 9 FSDM0565RB Typical Performance Characteristics (Continued) (These Characteristic Graphs are Normalized at Ta= 25°C) 1.2 1.0 Soft Start Time (Normalized to 25℃) 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 125 Junction Temperature (℃) Soft Start Time vs. Temp 10 FSDM0565RB Functional Description 1. Startup : In previous generations of Fairchild Power Switches (FPSTM) the Vcc pin had an external start-up resistor to the DC input voltage line. In this generation the startup resistor is replaced by an internal high voltage current source. At startup, an internal high voltage current source supplies the internal bias and charges the external capacitor (Cvcc) that is connected to the Vcc pin as illustrated in Figure 4. When Vcc reaches 12V, the FSDM0565RB begins switching and the internal high voltage current source is disabled. Then, the FSDM0565RB continues its normal switching operation and the power is supplied from the auxiliary transformer winding unless Vcc goes below the stop voltage of 8V. 2.1 Pulse-by-pulse current limit: Because current mode control is employed, the peak current through the Sense FET is limited by the inverting input of PWM comparator (Vfb*) as shown in Figure 5. Assuming that the 0.9mA current source flows only through the internal resistor (2.5R +R= 2.8 kΩ), the cathode voltage of diode D2 is about 2.5V. Since D1 is blocked when the feedback voltage (Vfb) exceeds 2.5V, the maximum voltage of the cathode of D2 is clamped at this voltage, thus clamping Vfb*. Therefore, the peak value of the current through the Sense FET is limited. VDC CVcc 2.2 Leading edge blanking (LEB) : At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the Rsense resistor would lead to incorrect feedback operation in the current mode PWM control. To counter this effect, the FSDM0565RB employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (TLEB) after the Sense FET is turned on. Vcc 3 6 Vstr Vcc Vref IFB OSC Istart Vref 8V/12V Vcc good Internal Bias Vo Vfb H11A817A CB Idelay 4 D1 D2 2.5R + Vfb* SenseFET R Gate driver KA431 - Figure 4. Internal startup circuit VSD OLP Rsense Figure 5. Pulse width modulation (PWM) circuit 2. Feedback Control : FSDM0565RB employs current mode control, as shown in Figure 5. An opto-coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. When the reference pin voltage of the KA431 exceeds the internal reference voltage of 2.5V, the H11A817A LED current increases, thus pulling down the feedback voltage and reducing the duty cycle. This event typically happens when the input voltage is increased or the output load is decreased. 3. Protection Circuit : The FSDM0565RB has several self protective functions such as over load protection (OLP), over voltage protection (OVP) and thermal shutdown (TSD). Because these protection circuits are fully integrated into the IC without external components, the reliability can be improved without increasing cost. Once the fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage, 8V, the protection is reset and the internal high voltage current source charges the Vcc capacitor via the Vstr pin. When Vcc reaches the UVLO start voltage,12V, the FSDM0565RB resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated (see Figure 6). 11 FSDM0565RB Vds Power on Fault occurs V FB Fault removed 6.0V Over load protection 2.5V Vcc T12= Cfb*(6.0-2.5)/Idelay 12V 8V T1 T2 t Figure 7. Over load protection t Normal operation Fault situation Normal operation Figure 6. Auto restart operation 3.1 Over Load Protection (OLP) : Overload is defined as the load current exceeding a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated in order to protect the SMPS. However, even when the SMPS is in the normal operation, the over load protection circuit can be activated during the load transition. In order to avoid this undesired operation, the over load protection circuit is designed to be activated after a specified time to determine whether it is a transient situation or an overload situation. Because of the pulse-by-pulse current limit capability, the maximum peak current through the Sense FET is limited, and therefore the maximum input power is restricted with a given input voltage. If the output consumes beyond this maximum power, the output voltage (Vo) decreases below the set voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (Vfb). If Vfb exceeds 2.5V, D1 is blocked and the 3.5uA current source starts to charge CB slowly up to Vcc. In this condition, Vfb continues increasing until it reaches 6V, when the switching operation is terminated as shown in Figure 7. The delay time for shutdown is the time required to charge CB from 2.5V to 6.0V with 3.5uA. In general, a 10 ~ 50 ms delay time is typical for most applications. 3.2 Over voltage Protection (OVP) : If the secondary side feedback circuit were to malfunction or a solder defect caused an open in the feedback path, the current through the opto-coupler transistor becomes almost zero. Then, Vfb climbs up in a similar manner to the over load situation, forcing the preset maximum current to be supplied to the SMPS until the over load protection is activated. Because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an over voltage protection (OVP) circuit is employed. In general, Vcc is proportional to the output voltage and the FSDM0565RB uses Vcc instead of directly monitoring the output voltage. If VCC exceeds 19V, an OVP circuit is activated resulting in the termination of the switching operation. In order to avoid undesired activation of OVP during normal operation, Vcc should be designed to be below 19V. 3.3 Thermal Shutdown (TSD) : The Sense FET and the control IC are built in one package. This makes it easy for the control IC to detect the heat generation from the Sense FET. When the temperature exceeds approximately 150°C, the thermal shutdown is activated. 4. Soft Start : The FSDM0565RB has an internal soft start circuit that increases PWM comparator inverting input voltage together with the Sense FET current slowly after it starts up. The typical soft start time is 10msec, The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. 12 FSDM0565RB 5. Burst operation : In order to minimize power dissipation in standby mode, the FSDM0565RB enters burst mode operation. As the load decreases, the feedback voltage decreases. As shown in Figure 8, the device automatically enters burst mode when the feedback voltage drops below VBURL(500mV). At this point switching stops and the output voltages start to drop at a rate dependent on standby current load. This causes the feedback voltage to rise. Once it passes VBURH(700mV) switching resumes. The feedback voltage then falls and the process repeats. Burst mode operation alternately enables and disables switching of the power Sense FET thereby reducing switching loss in Standby mode. Vo Voset VFB 0.7V 0.5V Ids Vds time Switching disabled T1 T2 T3 Switching disabled T4 Figure 8. Waveforms of burst operation 13 FSDM0565RB Typical application circuit Application LCD Monitor Output power 40W Input voltage Universal input (85-265Vac) Output voltage (Max current) 5V (2.0A) 12V (2.5A) Features • • • • • • High efficiency (>81% at 85Vac input) Low zero load power consumption (