FSEZ1216NY

FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET April 2009 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Features Constant-Voltage (CV) and Constant-Current (CC) Control without Secondary-Feedback Circuitry Green Mode: Frequency Reduction at Light-Load Fixed PWM Frequency at 42kHz with Frequency Hopping to Reduce EMI Cable Voltage Drop Compensation in CV Mode Low Startup Current: 10μA Low Operating Current: 3.5mA Peak-Current-Mode Control in CV Mode Cycle-by-Cycle Current Limiting VDD Over-Voltage Protection with Auto-Restart VDD Under-Voltage Lockout (UVLO) Gate Output Maximum Voltage Clamped at 18V Fixed Over-Temperature Protection with Latch DIP-8 Package Available Description The primary-side PWM integrated Power MOSFET, FSEZ1216, significantly simplifies power supply design that requires CV and CC regulation capabilities. FSEZ1216 controls the output voltage and current precisely only with the information in the primary side of the power supply, not only removing the output current sensing loss, but also eliminating all secondary feedback circuitry. The green-mode function with a low startup current (10µA) maximizes the light load efficiency so the power supply can meet stringent standby power regulations. Compared with conventional secondary side regulation approach, the FSEZ1216 can reduce total cost, component count, size, and weight, while simultaneously increasing efficiency, productivity, and system reliability. A typical output CV/CC characteristic envelope is shown in Figure 1. Applications Battery Chargers for Cellular Phones, Cordless Phones, PDA, Digital Cameras, Power Tools Replaces Linear Transformer and RCC SMPS Offline High Brightness (HB) LED Drivers Figure 1. Typical Output V-I Characteristic Ordering Information Part Number Operating Temperature Range MOSFET BVDSS 600V MOSFET RDS.ON 9.3Ω (Typical) Eco Status Green Package 8-Lead, Dual Inline Package (DIP-8) Packing Method Tube FSEZ1216NY -40°C to +105°C For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Application Diagram CSN 2 Bridge Rectifier Diode CDL RSN 2 VO VDL + RSTAR T DSN DDD AC Line RCS 1 2 COMR 3 COMI RSN1 CSN1 NP NS DR CO IO CDD FSEZ1216 CS DRAIN 8 GND 7 VDD 6 VS 5 NA RS1 CCOMR RCOMR 4 COMV RS2 CC OM I RC OM I CCOMV RCOMV CS Figure 2. Typical Application Internal Block Diagram VDD + OVP 6 28V - Auto Restart Protection + Internal Bias Brownout OTP Latch Protection 8 DRAIN 16V/5V OSC with Frequency Hopping SQ + RQ + Soft-Driver PWM Comparator PWM Comparator 1.3V Leading-Edge Blanking PWM Comparator Slope Compensation IO Estimator 2.5V Brownout Protection t DIS Detector - EA_I GND 7 3 COMI EA_V 4 COMV Figure 3. © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 Functional Block Diagram www.fairchildsemi.com 2 - Green Mode Controller Cable Drop Compensation Temperature Compensation COMR + - 1 CS + + - 5 VS VO Estimator 2 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Marking Information F- Fairchild Logo Z- Plant Code X- 1-Digit Year Code Y- 1-Digit Week Code TT- 2-Digits Die Run Code T- Package Type (N=DIP) P- Z: Pb Free, Y: Green Package M- Manufacture Flow Code Figure 4. Top Mark Pin Configuration CS COMR COMI COMV Figure 5. DRAIN GND VDD VS Pin Configuration Pin Definitions Pin # 1 2 3 4 5 6 7 8 Name CS COMR COMI COMV VS VDD GND DRAIN Description Current Sense. This pin connects a current-sense resistor to sense the MOSFET current for peak-current-mode control in CV mode and provides for output-current regulation in CC mode. Cable Compensation. This pin connects a capacitor between COMR and GND for compensation voltage drop due to output cable loss in CV mode. Constant Current Loop Compensation. This pin connects a capacitor and a resistor between COMI and GND for compensation current loop gain. Constant Voltage Loop Compensation. This pin connects a capacitor and a resistor between COMV and GND for compensation voltage loop gain. Voltage Sense. This pin detects the output voltage information and discharge time based on voltage of auxiliary winding. This pin connects two divider resistors and one capacitor. Power Supply. The power supply pin for the IC operating current and MOSFET driving current. This pin is connects to an external VDD capacitor (typically 10μF). The threshold voltages for startup and turn-off are 16V and 5V, respectively. Ground. Drain. This pin is the high-voltage power MOSFET drain. © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 3 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VVDD VVS VCS VCOMV VCOMI VDS ID IDM EAS IAR PD ΘJA ΘJC TJ TSTG TL ESD DC Supply Voltage (1) Parameter VS Pin Input Voltage CS Pin Input Voltage Voltage Error Amplifier Output Voltage Voltage Error Amplifier Output Voltage Drain-Source Voltage Continuous Drain Current Pulsed Drain Current Single Pulse Avalanche Energy Avalanche Current Power Dissipation (TA＜50°C) Thermal Resistance Junction-to-Air Thermal Resistance Junction-to-Case Operating Junction Temperature Storage Temperature Range Lead Temperature (Wave Soldering or IR, 10 Seconds) Electrostatic Discharge Capability, Human Body Model, JEDEC: JESD22-A114 Electrostatic Discharge Capability, Charged Device Model, JEDEC: JESD22-C101 TC=25°C TC=100°C Min. -0.3 -0.3 -0.3 -0.3 Max. 30 7.0 7.0 7.0 7.0 600 1.0 0.6 4 33 1 800 113 67 +150 Unit V V V V V V A A mJ A mW °C/W °C/W °C °C °C KV V -55 +150 +260 2.5 1250 Note: 1. All voltage values, except differential voltages, are given with respect to GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature Conditions Min. -40 Typ. Max. +105 Unit °C © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 4 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Electrical Characteristics VDD=15V and TA=25°C unless otherwise specified. Symbol VDD Section VOP VDD-ON VDD-OFF IDD-ST IDD-OP IDD-GREEN VDD-OVP tD-VDDOVP Parameter Continuously Operating Voltage Turn-On Threshold Voltage Turn-Off Threshold Voltage Startup Current Operating Current Green Mode Operating Supply Current VDD Over-Voltage Protection Level VDD Over-Voltage Protection Debounce Time Conditions Min. Typ. Max. 25 Units V V V μA mA mA V μs 15 4.5 0< VDD < VDD-ON-0.16V VDD=20V, fS=fOSC, VVS=2V, VCS=3V, CL=1nF VDD=20V, VVS=2.7V, fS=fOSC-N-MIN, VCS=0V, CL=1nF, VCOMV=0V VCS=3V, VVS=2.3V, fs= fOSC, VVS=2.3V 27 100 0 16 5.0 1.6 3.5 1 28 250 17 5.5 10.0 5.0 2 29 400 Oscillator Section Center Frequency fOSC tFHR fOSC-N-MIN fOSC-CM-MIN fDV fDT Frequency Frequency Hopping Range TA=25°C TA=25°C TA=25°C VVS=2.7V, VCOMV=0V VVS=2.3V, VCS=0.5V VDD=10V to 25V TA=-40°C to +85°C 39 ±1.8 42 ±2.6 3 550 20 5 15 45 ±3.6 KHz ms Hz KHz % % Frequency Hopping Period Minimum Frequency at No Load Minimum Frequency at CCM Frequency Variation vs. VDD Deviation Frequency Variation vs. Temperature Deviation Voltage-Sense Section IVS-UVP Itc VBIAS-COMV Sink Current for Brownout Protection IC Compensation Bias Current Adaptive Bias Voltage Dominated by VCOMV VCOMV=0V, TA=25°C, RVS=20KΩ RVS=20KΩ 180 9.5 1.4 μA μA V Current-Sense Section tPD tMIN-N tMINCC DSAW VTH Propagation Delay to GATE Output Minimum On Time at No Load Minimum On Time in CC Mode Duty Cycle of SAW Limiter Threshold Voltage for Current Limit VVS=-0.8V, RS=2KΩ, VCOMV=1V VVS=0V, VCOMV=2V 100 1100 400 40 1.3 200 ns ns ns % V Continued on following page… © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 5 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Electrical Characteristics VDD=15V and TA=25°C unless otherwise specified. Symbol VVR VN VG IV-SINK IV-SOURCE VV-HGH VIR II-SINK II-SOURCE VI-HGH Parameter Reference Voltage Conditions Min. 2.475 Typ. 2.500 2.8 0.8 90 90 Max. 2.525 Units V V V μA μA V Voltage-Error-Amplifier Section Green Mode Starting Voltage on fS=fOSC-2KHz, VVS=2.3V COMV Pin Green Mode Ending Voltage on COMV Pin Output Sink Current Output Source Current Output High Voltage Reference Voltage Output Sink Current Output Source Current Output High Voltage VCS=3V, VCOMI=2.5V VCS=0V, VCOMI=2.5V VCS=0V 4.5 fS=1KHz VVS=3V, VCOMV=2.5V VVS=2V, VCOMV=2.5V VVS=2.3V 4.5 2.475 2.500 55 55 2.525 Current-Error-Amplifier Section V μA μA V Cable Compensation Section VCOMR Variation Test Voltage on COMR RCOMR=100k Pin for Cable Compensation Maximum Duty Cycle Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Maximum Continuous DrainSource Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current Static Drain-Source OnResistance Drain-Source Leakage Current Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance VGS=0V, VDS=25V, fS=1MHz (2,3) 0.735 V Internal MOSFET Section DCYMAX BVDSS ∆BVDSS /∆TJ IS ISM RDS(ON) IDSS tD-ON tr tD-OFF tf CISS COSS 75 ID=250μA, VGS=0V ID=250μA, Referenced to 25°C 600 0.6 1 4 ID=0.5A, VGS=10V VDS=600V, VGS=0V, TC=25°C VDS=480V, VGS=0V, TC=100°C VDS=300V, ID=1.1A, RG=25Ω 7 21 13 27 130 19 9.3 11.5 1 10 24 52 36 64 170 25 % V V/°C A A Ω μA ns ns ns ns pF pF Over-Temperature-Protection Section TOTP Threshold Temperature for (4) OTP +140 °C Notes: 2. Pulse test: pulse width ≦ 300µs, duty cycle ≦ 2%. 3. Essentially independent of operating temperature. 4. When over-temperature protection is activated, the power system enters latch mode and output is disabled. © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 6 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Typical Performance Characteristics 17 5.5 16.6 5.3 16.2 VDD-OFF (V) -40 -30 -15 0 25 50 75 85 100 125 VDD-ON (V) 5.1 15.8 4.9 15.4 4.7 15 4.5 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 6. Turn-On Threshold Voltage (VDD-ON) vs. Temperature Figure 7. Turn-Off Threshold Voltage (VDD-OFF) vs. Temperature 4.5 45 44 43 42 41 40 39 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 25 50 75 85 100 125 4.1 IDD-OP (mA) 3.7 3.3 2.9 2.5 Temperature (ºC) fOSC (KHz) Temperature (ºC) Figure 8. Operating Current (IDD-OP) vs. Temperature Figure 9. Center Frequency (fOSC) vs. Temperature 2.525 2.525 2.515 2.515 VVR (V) 2.495 VIR (V) -40 -30 -15 0 25 50 75 85 100 125 2.505 2.505 2.495 2.485 2.485 2.475 2.475 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 10. Reference Voltage (VVR) vs. Temperature Figure 11. Reference Voltage (VIR) vs. Temperature © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 7 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Typical Performance Characteristics (Continued) 600 25 560 23 520 fOSC-CM-MIN (KHz) -40 -30 -15 0 25 50 75 85 100 125 fOSC-N-MIN (Hz) 21 480 19 440 17 400 15 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 12. Minimum Frequency at No Load (fOSC-N-MIN) vs. Temperature Figure 13. Minimum Frequency at CCM (fOSC-CM-MIN) vs. Temperature 30 25 1000 950 900 850 800 750 700 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 25 50 75 85 100 125 SG (KHz/V) 15 10 5 0 Temperature (ºC) tMIN-N (ns) 20 Temperature (ºC) Figure 14. Green Mode Frequency Decreasing Rate (SG) vs. Temperature Figure 15. Minimum On Time at No Load (tMIN-N) vs. Temperature 5 1 4 0.8 VN (V) 2 VG (V) 3 0.6 0.4 1 0.2 0 -40 -30 -15 0 25 50 75 85 100 125 0 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 16. Green Mode Starting Voltage on COMV Pin (VN) vs. Temperature Figure 17. Green Mode Ending Voltage on COMV Pin (VG) vs. Temperature © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 8 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Typical Performance Characteristics (Continued) 95 95 92 91 89 IV-SOURCE (µA) -40 -30 -15 0 25 50 75 85 100 125 IV-SINK (µA) 87 86 83 83 79 80 75 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 18. Output Sink Current (IV-SINK) vs. Temperature Figure 19. Output Source Current (IV-SOURCE) vs. Temperature 65 65 62 62 59 II-SOURCE (µA) -40 -30 -15 0 25 50 75 85 100 125 II-SINK (µA) 59 56 56 53 53 50 50 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 20. Output Sink Current (II-SINK) vs. Temperature Figure 21. Output Source Current (II-SOURCE) vs. Temperature 2 80 1.6 76 1.2 DCYMAX (%) -40 -30 -15 0 25 50 75 85 100 125 VCOMR (V) 72 0.8 68 0.4 64 0 60 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 22. Variation Test Voltage on COMR Pin for Cable Compensation (VCOMR) vs. Temperature Figure 23. Maximum Duty Cycle (DCYMAX) vs. Temperature © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 9 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Functional Description Figure 24 shows the basic circuit diagram of primaryside regulated flyback converter, with typical waveforms shown in Figure 25. Generally, discontinuous conduction mode (DCM) operation is preferred for primary-side regulation since it allows better output regulation. The operation principles of DCM flyback converter are as follows: During the MOSFET ON time (tON), input voltage (VDL) is applied across the primary-side inductor (Lm). Then MOSFET current (Ids) increases linearly from zero to the peak value (Ipk). During this time, the energy is drawn from the input and stored in the inductor. When the MOSFET is turned off, the energy stored in the inductor forces the rectifier diode (D) to turn on. While the diode is conducting, the output voltage (VO), together with diode forward voltage drop (VF), are 2 applied across the secondary-side inductor (Lm×Ns / 2 Np ) and the diode current (ID) decreases linearly from the peak value (Ipk× Np/Ns) to zero. At the end of inductor current discharge time (tDIS), all the energy stored in the inductor has been delivered to the output. When the diode current reaches zero, the transformer auxiliary winding voltage (VW) begins to oscillate by the resonance between the primary-side inductor (Lm) and the effective capacitor loaded across MOSFET. During the inductor current discharge time, the sum of output voltage and diode forward voltage drop is reflected to the auxiliary winding side as (VO+VF)× NA/NS. Since the diode forward voltage drop decreases as current decreases, the auxiliary winding voltage reflects the output voltage best at the end of diode conduction time where the diode current diminishes to zero. By sampling the winding voltage at the end of the diode conduction time, the output voltage information can be obtained. The internal error amplifier for output voltage regulation (EA_V) compares the sampled voltage with internal precise reference to generate error voltage (VCOMV), which determines the duty cycle of the MOSFET in CV mode. Meanwhile, the output current can be estimated using the peak drain current and inductor current discharge time since output current is same as the average of the diode current in steady state. The output current estimator picks up the peak value of the drain current with a peak detection circuit and calculates the output current using the inductor discharge time (tDIS) and switching period (tS). These output information is compared with internal precise reference to generate error voltage (VCOMI), which determines the duty cycle of the MOSFET in CC mode. Among the two error voltages, VCOMV and VCOMI, the smaller actually determines the duty cycle. During constant voltage regulation mode, VCOMV determines the duty cycle while VCOMI is saturated to HIGH. During constant current regulation mode, VCOMI determines the duty cycle while VCOMV is saturated to HIGH. Np:Ns D + V DL Lm + VF + VO L O A D ID IO VAC Ids EA_I V COMI PWM Control V COMV EA_V IO Estimator Ref t DIS Detector VO Estimator Ref CS RCS VS VDD RS1 RS2 NA + Vw - Primary-Side Regulation Controller Figure 24. Simplified PSR Flyback Converter Circuit Id s (MOSFET Drain-to-Source Current) I pk ID (Diode Current) I pk • NP NS I D .avg = I o VW (Auxiliary Winding Voltage) VF • NA NS VO • NA NS t ON t S t DI S Figure 25. Key Waveforms of DCM Flyback Converter © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 10 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Cable Voltage Drop Compensation When it comes to cellular phone charger applications, the actual battery is located at the end of cable, which causes, typically, several percent of voltage drop on the actual battery voltage. FSEZ1216 has a programmable cable voltage drop compensation, which provides a constant output voltage at the end of the cable over the entire load range in CV mode. As load increases, the voltage drop across the cable is compensated by increasing the reference voltage of voltage regulation error amplifier. The amount of compensation is programmed by the resistor on the COMR pin. The relationship between the amount of compensation and the COMR resistor is shown in Figure 26. 15 14 13 12 11 Switching Frequen cy 42kHz Dee p Green Mode 550H z 0.8V Green Mode Normal Mode 2.8V V COMV Figure 27. Switching Frequency in Green Mode Compensation Percentage (%) 10 9 8 7 6 5 4 3 2 1 10 20 30 40 50 60 RCOMR (k ) 70 80 90 100 Frequency Hopping EMI reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. FSEZ1216 has an internal frequency hopping circuit that changes the switching frequency between 39.4kHz and 44.6kHz with a period of 3ms, as shown in Figure 28. Gate Drive Signal t Figure 26. Cable Voltage Drop Compensation s Temperature Compensation Built-in temperature compensation provides constant voltage regulation over wide a range of temperature variation. This internal compensation current compensates the forward-voltage drop variation of the secondary-side rectifier diode. t s t fs 44.6kHz 42.0kHz 39.4kHz s Green-Mode Operation The FSEZ1216 uses voltage regulation error amplifier output (VCOMV) as an indicator of the output load and modulates the PWM frequency, as shown in Figure 27, such that the switching frequency decreases as load decreases. In heavy load conditions, the switching frequency is fixed at 42KHz. Once VCOMV decreases below 2.8V, the PWM frequency starts to linearly decrease from 42KHz to 550Hz to reduce the switching losses. As VCOMV decreases below 0.8V, the switching frequency is fixed at 550Hz and FSEZ1216 enters deep green mode, where the operating current reduces to 1mA, further reducing the standby power consumption. 3ms Figure 28. Frequency Hopping t © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 11 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Leading-Edge Blanking (LEB) At the instant the MOSFET is turned on, there is a highcurrent spike through the MOSFET, caused by primaryside capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the RCS resistor can lead to premature turn-off of MOSFET. FSEZ1216 employs an internal leading-edge blanking (LEB) circuit. To inhibit the PWM comparator for a short time after the MOSFET is turned on. External RC filtering is not required. enables and disables the switching of the MOSFET until the fault condition is eliminated (see Figure 30). Meanwhile, OTP is latch mode protection, which is reset when VDD is fully discharged by un-plugging the AC power line. Power On Fault Occurs Fault Removed VDS Startup Figure 29 shows the typical startup circuit and transformer auxiliary winding for a FSEZ1216 application. Before FSEZ1216 begins switching, it consumes only startup current (typically 10μA) and the current supplied through the startup resistor charges the VDD capacitor (CDD). When VDD reaches turn-on voltage of 16V (VDD-ON), FSEZ1216 begins switching, and the current consumed by FSEZ1216 increases to 3.5mA. Then, the power required for FSEZ1216 is supplied from the transformer auxiliary winding. The large hysteresis of VDD provides more holdup time, which allows using a small capacitor for VDD. VDD 16V 5V Operating Current VD L + CD L RSTAR T DD D Np 3.5mA 10µA Normal Operation Fault Situation Normal Operation Figure 30. Auto-Restart Operation AC Line CD D NA FSEZ1216 1 2 3 4 CS COMR COMI COMV DRAIN 8 SGND VDD VS 7 6 5 RS1 RS2 VDD Over-Voltage Protection (OVP) VDD over-voltage protection prevents damage from overvoltage conditions. If the VDD voltage exceeds 28V by open feedback condition, OVP is triggered. The OVP has a de-bounce time (typcal 250µs) to prevent false trigger by switching noise. It also protects other switching devices from over voltage. Over-Temperature Protection (OTP) A built-in temperature-sensing circuit shuts down PWM output if the junction temperature exceeds 140°C. Figure 29. Startup Circuit Brownout Protection FSEZ1216 detects the line voltage using auxiliary winding voltage since the auxiliary winding voltage reflects the input voltage when the MOSFET is turned on. The VS pin is clamped at 1.15V while the MOSFET is turned on and brownout protection is triggered if the current out of the VS pin is less than IVS-UVP (typical 180μA) during the MOSFET conduction. Pulse-by-Pulse Current Limit When the sensing voltage across the current sense resistor exceeds the internal threshold of 1.4V, the MOSFET is turned off for the remainder of switching cycle. In normal operation, the pulse-by-pulse current limit is not triggered since the peak current is limited by the control loop. www.fairchildsemi.com 12 Protections The FSEZ1216 has several self-protective functions, such as Over-Voltage Protection (OVP), OverTemperature Protection (OTP), and brownout protection. All the protections except OTP are implemented as auto-restart mode. Once the fault condition occurs, switching is terminated and the MOSFET remains off. This causes VDD to fall. When VDD reaches the VDD turn-off voltage of 5V, the current consumed by FSEZ1216 reduces to the startup current (typically 10µA) and the current supplied startup resistor charges the VDD capacitor. When VDD reaches the turnon voltage of 16V, FSEZ1216 resumes its normal operation. In this manner, the auto-restart alternately © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Typical Application Circuit (Primary-Side Regulated Flyback Charger) Application Cell Phone Charger Fairchild Devices FSEZ1216 Input Voltage Range 90~265VAC Output 5V/0.78A (3.9W) Features High efficiency (>66% at full load) meeting Energy StarSM V2.0 and CEC regulation Low standby power consumption (Pin=0.095W for 115VAC and Pin=0.138W for 230VAC) Tight output regulation (CV:±5%, CC:±7%) 74 72 115V60Hz (68.7% avg) 6 5 70 Output Voltage (V) 4 AC90V AC230V AC120V AC264V Efficiency (%) 68 66 64 230V50Hz (66.9% avg) 3 66.3% : Energy Star V2.0 (Nov. 2008) 2 62 1 62.2% : CEC (2008) 0 25 50 Load (%) 75 100 0 100 200 300 400 500 600 700 800 900 Output Current (mA) Figure 31. Measured Efficiency and Output Regulation 1nF 30Ω CSN2 1mH RSN2 LP 15µH IO VO RPL 1kΩ SB260 + 1N4007 1N4007 1kΩ RSN1 VDL RSTART 2MΩ 100kΩ CSN1 1nF DR N1 N3 CO 470µF CDL2 1N4007 1N4007 4.7µF CDL1 4.7µF CP 220µF RDAMP 270Ω 1N4007 DSN 1N4007 4.7µH AC Line DDD CDD 10µF N2 FSEZ1216 1 2 100kΩ CS COMR COMI COMV DRAIN SGND VDD VS 8 7 6 5 RS2 24.9kΩ RS1 115kΩ 3 4 RCS 1.4Ω RCOMR CCOMR 1µF 10nF 68nF CCOMI 200kΩRCOMI CCOMV RCOMV 43kΩ CS 47pF Figure 32. Schematic of Typical Application Circuit © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 13 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Typical Application Circuit (Continued) Transformer specification Core: EE16 Bobbin: EE16 Pin Primary-Side Inductance Primary-Side Effective Leakage 1－3 1－8 Specifications 2.3mH ± 5% 65μH ± 5%. 100kHz, 1V Remark Short one of the secondary windings © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 14 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Physical Dimensions 9.83 9.00 6.67 6.096 8.255 7.61 5.08 MAX 3.683 3.20 7.62 0.33 MIN (0.56) 2.54 3.60 3.00 0.56 0.355 1.65 1.27 7.62 0.356 0.20 9.957 7.87 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994 E) DRAWING FILENAME AND REVSION: MKT-N08FREV2. Figure 33. 8-Lead, Dual Inline Package (DIP-8) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 15 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 16