FSSD06BQX

FSSD06 — SD/SDIO and MMC Two-Port Multiplexer September 2008 FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Features On Resistance Typically 4Ω, VDDH=2.7V Ftoggle: > 120MHz Low On Capacitance: 9pF Typical Low Power Consumption: 1µA Maximum Conforms to Secure Digital (SD), Secure Digital I/O (SDIO), and Multimedia Card (MMC) Specifications Supports 1-Bit / 4-Bit Host Controllers (VDDH=1.65V to 3.6V) Communicating with High-Voltage (2.7-3.6V) and Dual-Voltage Cards (1.65-1.95V, 2.7-3.6V) Description The FSSD06 is a two-port multiplexer that allows Secure Digital (SD), Secure Digital I/O (SDIO), and Multimedia Card (MMC) host controllers to be expanded out to multiple cards or peripherals. This configuration enables the CMD, CLK, and D[3:0] signals to be multiplexed to dual-card peripherals. It is optimized for 1-bit / 4-bit SD / MMC applications. The architecture includes the necessary bi-directional data and command transfer capability for single highvoltage cards or dual-voltage supply cards. The clock path for the FSSD06 is a uni-directional buffer with an integrated pull-up for high-impedance mode. Typical applications involve switching in portables and consumer applications: cell phones, digital cameras, home theater monitors, portable GPS units, and printers. - VDDH=1.65 to 3.6V, VDDC1/C2=VDDH to 3.6V 24-Lead MLP (3.5 x 4.5mm) and UMLP Packages Applications Cell Phone, PDA, Digital Camera, Portable GPS LCD Monitor, Home Theater PC/TV, All-in-One Printer IMPORTANT NOTE: For additional performance information, please contact analogswitch@fairchildsemi.com. Analog Symbol Diagram VDDC1 VDDC2 VDDH 5 DAT[0:3], CMD 5 5 2DAT[0:3], 2CMD Control /OE S 1DAT[0:3], 1CMD V DD C1 V DD C 2 RP U RPU CLK 1CLK 2CLK GND Figure 1. Analog Symbol Diagram Ordering Information Part Number FSSD06BQX FSSD06UMX Operating Temperature Range -40°C to +85°C -40°C to +85°C Eco Status Green Green Package Description 24-Lead Molded Leadless Package (MLP), JEDEC MO-220, 3.5 x 4.5mm 24-Lead Ultrathin Molded Leadless Package (UMLP) Packing Method Tape & Reel Tape & Reel For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 www.fairchildsemi.com CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Pin Configuration 1DAT[2] 1DAT[3] 1CMD 1DAT[2] 1DAT[3] VDDC1 19 18 17 16 15 14 13 11 1CLK 1DAT[0] 1DAT[1] 2DAT[2] 2DAT[3] 2CMD 12 DAT[2] 2 1 24 23 22 21 20 19 18 17 16 15 24 /OE 23 22 21 DAT[2] DAT[3] CMD VDDH GND CLK DAT[0] DAT[1] 3 4 5 6 7 8 9 10 11 12 13 14 VDDC1 1CLK DAT[3] CMD 1 2 3 4 5 6 1DAT[0] 1DAT[1] 2DAT[2] 2DAT[3] 2CMD VDDC2 VDDH GND CLK DAT[0] 7 8 9 10 1CMD 20 /OE DAT[1] S 2DAT[1] 2DAT[0] 2CLK VDDC2 Figure 2. S 2DAT[1] MLP Pin Assignments 2DAT[0] 2CLK Figure 3. UMLP Pin Assignments Pin Definitions Name VDDH VDDC1, VDDC2 /OE S 1DAT[3:0], 2DAT[3:0], 1CMD, 2CMD DAT[3:0], CMD CLK, 1CLK, 2CLK Description Power Supply (Host ASIC) Power Supply (SDIO Peripheral Card Ports) Output Enable (Active Low) Select Pin SDIO Card Ports SDIO Common Ports Clock Path Ports Truth Table /OE LOW LOW HIGH S LOW HIGH X Function CMD, CLK, DAT[3:0] connected to 1CMD, 1CLK, 1DAT[3:0]; 2CLK pulled HIGH via RPU CMD, CLK, DAT[3:0] connected to 2CMD, 2CLK, 2DAT[3:0]; 1CLK pulled HIGH via RPU All Ports High Impedance; 1CLK, 2CLK pulled HIGH via RPU © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 www.fairchildsemi.com 2 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Typical Application Diagram VDDH 1.65 – 3.60V VDDC1 FSSD06 RT GND VDD H to 3.6V CMD, DAT[3:0] 5 1CMD, 1DAT[3:0] 5 1CLK Processor Secure Data / Multimedia Card 2:1 Peripheral Expander WiFi, Bluetooth, MMC or SD Module VDDC2 CLK RT GND 2CMD, 2DAT[3:0] 5 2CLK VDD H to 3.6V Note : External resistors (R T) are recommended if card supplies are allowed to float in the application. The resistors should be >500K to minimize power consumption. GND /OE S WiFi, , Bluetooth, MMC or SD Module Figure 4. Typical Application Diagram Functional Description The FSSD06 enables sharing the ASIC/baseband processor SDIO port(s) to two peripheral cards, providing bi-directional support for dual-voltage SD/SDIO or MMC cards available in the marketplace. Each SDIO port of the FSSD06 has its own supply rail, allowing peripheral cards with different supplies to be interfaced to the host. The peripheral card supplies must be equal or greater than the host to minimize power consumption. The independent VDDH, VDDC1, and VDDC2 are defined by the supplies connected from the application Power Management ICs (PMICs) to the FSSD06. The clock path is a uni-directional buffered path rather than a bi-directional switch port. CLK Bus The 1CLK and 2CLK outputs are bi-state buffer architectures, rather than a switch I/O, to ensure 52MHz incident wave switching. When there is no communication on the bus (IDLE), the FSSD06 can be disabled with the /OE pin. When this pin is pulled HIGH, the nCLK outputs are also pulled HIGH. Along with nCMD, nDAT[3:0] goes high-impedance to ensure that the CLK path between the FSSD06 and the peripheral does not float. IDLE State CMD/DAT Bus “Parking” The SD and MMC card specifications were written for a direct point-to-point communication between host controller and card. The introduction of the FSSD06 in that path, as an expander, requires that the functional operation and system latency not be impacted by the FSSD06 switch characteristics. Since there are various card formats, protocols, and configurable controllers, a /OE pin is available to facilitate a fast IDLE transition for the nCMD/nDAT[3:0] outputs. Some controllers, rather than simply placing CMD/DAT into high-impedance mode, may pull their outputs HIGH for a clock cycle prior to going into high-impedance mode (referred to as “parking” the output). Some legacy controllers pull their outputs HIGH versus high impedance. If the /OE pin is left LOW and the controller places the CMD/DAT[3:0] outputs into high impedance, the nCMD/nDAT[3:0] output rise time is a function of the RC time constant through the switch path. It is recommended that the host controller pull CMD and DAT[3:0] HIGH for one cycle before pulling /OE HIGH. This facilitates parking all nCMD/nDAT[3:0] outputs HIGH before putting the switch I/Os in high impedance. www.fairchildsemi.com 3 CMD, DAT Bus Pull-ups The 1CMD, 2CMD, 1DAT[3:0], and 2DAT[3:0] ports do not have, internally, the system pull-up resistors as defined in the MMC or SD card system bus specifications. The system bus pull-up must be added external to the FSSD06. The value, within the specific specification limits, is a function of the individual application and type of card or peripheral connected. For SD card applications, the RCMD and RDAT pull-ups should be between 10kΩ and 100kΩ. For MMC applications, the RCMD pull-ups should be between 4.7kΩ and 100kΩ and the RDAT pull-ups between 50kΩ and 100kΩ. The card-side 1CMD, 2CMD, 1DAT[3:0], and 2DAT[3:0] outputs have a circuit that facilitates incident wave switching, so the external pull-up resistors ensure retention of the output high level. The /OE pin can be used to place the 1CMD, 2CMD, 1DAT[3:0] and 2DAT[3:0] into high-impedance mode when the system enters IDLE state (see IDLE State CMD/DAT Bus “Parking”). © 2007 Fairchild Semiconductor Corporation FSSD06 Rev. 1.0.3 CONFIDENTIAL AND PROPRIETARY — DO NOT DISTRIBUTE FSSD06 — SD/SDIO and MMC Two-Port Multiplexer Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDDH VDDC1,VDDC2 VSW (1) Parameter Supply Voltage Supply Voltage Switch I/O Voltage Conditions Min. -0.5 -0.5 Max. 4.6 4.6 VDDx + 0.3V (4.6V maximum) VDDx + 0.3V (4.6V maximum) 4.6 4.6 VDDx + 0.3V (4.6V maximum) -50 50 100 (2) (2) (2) Unit V V V V V V V mA mA mA °C °C °C kV kV 1DAT[3:0], 2DAT[3:0], 1CMD, 2CMD Pins DAT[3:0], CMD Pins -0.5 -0.5 -0.5 -0.5 -0.5 VCNTRL VCLKO (1) Control Input Voltage CLK Input Voltage CLK Output Voltage Input Clamp Diode Current Switch I/O Current Peak Switch Current Storage Temperature Range Max Junction Temperature Lead Temperature Human Body Model (JEDEC: JESD22-A114) S, /OE CLK 1CLK, 2CLK (1) VCLKI (1) IINDC ISW ISWPEAK TSTG TJ TL SDIO Continuous SDIO Pulsed at 1ms Duration,