FST162861

FST162861

  • 厂商:

    FAIRCHILD(仙童半导体)

  • 封装:

  • 描述:

    FST162861 - 20-Bit Bus Switch with 25ohm Series Resistors in Outputs - Fairchild Semiconductor

  • 详情介绍
  • 数据手册
  • 价格&库存
FST162861 数据手册
FST162861 20-Bit Bus Switch with 25: Series Resistors in Outputs March 2000 Revised June 2005 FST162861 20-Bit Bus Switch with 25: Series Resistors in Outputs General Description The Fairchild Switch FST162861 provides 20-bits of highspeed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. The device is organized as a 10-bit or 20-bit bus switch. When OE1 is LOW, the switch is ON and Port 1A is connected to Port 1B. When OE2 is LOW, Port 2A is connected to Port 2B. When OEX is HIGH, a high impedance state exists between the A and B ports. The FST162861 has an equivalent 25: series resistors to reduce signal-reflection noise, eliminating the need for external terminating resistors. Features s 25: switch connection between two ports. s Minimal propagation delay through the switch. s Low lCC. s Zero bounce in flow-through mode. s Control inputs compatible with TTL level. Ordering Code: Order Number FST162861MTD (Note 1) FST162861MTDX_NL (Note 2) Package Number MTD48 MTD48 Package Description 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pb-Free 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 1: D evices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Note 2: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only. © 2005 Fairchild Semiconductor Corporation DS500319 www.fairchildsemi.com FST162861 Logic Diagram Connection Diagram Truth Table Inputs OE1 L L H H OE2 L H L H Inputs/Outputs 1A, 1B 1A 1A Z Z 1B 1B 2A Z 2A, 2B 2A Z 2B 2B Pin Descriptions Pin Name OE1, OE2 1A, 2A 1B, 2B Description Bus Switch Enables Bus A Bus B www.fairchildsemi.com 2 FST162861 Absolute Maximum Ratings(Note 3) Supply Voltage (VCC) DC Switch Voltage (VS) (Note 4) DC Input Voltage (VIN) (Note 5) DC Input Diode Current (lIK) VIN  0V DC Output (IOUT) Current DC VCC/GND Current (ICC/IGND) Storage Temperature Range (TSTG) 0.5V to 7.0V 0.5V to 7.0V 0.5V to 7.0V 50mA 128mA Recommended Operating Conditions (Note 6) Power Supply Operating (VCC) Input Voltage (VIN) Output Voltage (VOUT) Input Rise and Fall Time (tr, tf) Switch Control Input Switch I/O Free Air Operating Temperature (TA) 0nS/V to 5nS/V 0nS/V to DC -40 qC to 85 qC 4.0V to 5.5V 0V to 5.5V 0V to 5.5V r100mA 65qC to 150 qC Note 3: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 4: VS is the voltage observed/applied at either the A or B Port across the switch. Note 5: The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Note 6: Unused control inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIK VIH VIL II IOZ RON Parameter Clamp Diode Voltage HIGH Level Input Voltage LOW Level Input Voltage Input Leakage Current OFF-STATE Leakage Current Switch ON Resistance (Note 8) VCC (V) 4.5 4.0–5.5 4.0–5.5 5.5 0 5.5 4.5 4.5 4.5 4.0 ICC Quiescent Supply Current Increase in ICC per Input 5.0V and TA TA Min 40 qC to 85 qC Typ (Note 7) Max Units V V 0.8 V IIN Conditions 1.2 2.0 18mA r1.0 r1.0 r1.0 20 20 20 20 26 27 28 30 38 40 48 48 3 2.5 PA PA PA : : : : PA mA 0 d VIN d 5.5V VIN VIN VIN VIN VIN VIN 5.5V 0V, IIN 0V, IIN 2.4V, IIN 2.4V, IIN 64mA 30mA 15mA 15mA 0 0 d A, B d VCC 5.5 5.5 25qC VCC or GND, IOUT ' ICC One input at 3.4V Other inputs at VCC or GND Note 7: Typical values are at VCC Note 8: M easured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A or B) pins. 3 www.fairchildsemi.com FST162861 AC Electrical Characteristics CL Symbol Parameter VCC Min tPHL,tPLH tPZH, tPZL tPHZ, tPLZ Prop Delay Bus to Bus (Note 9) Output Enable Time Output Disable Time 1.0 1.0 TA 40 qC to 85 qC, 50 pF, RU RD 500: VCC Min 4.0V Max 1.25 5.5 6.3 ns ns ns VI VI VI 6.0 VI VI OPEN 7V for tPZL OPEN for tPZH 7V for tPLZ OPEN for tPHZ Figures 1, 2 Figures 1, 2 Figures 1, 2 Units Conditions Figure No. 4.5 – 5.5V Max 1.25 5.3 Note 9: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance). Capacitance Symbol CIN CI/O Note 10: TA (Note 10) Parameter Typ 3.5 6.0 Max Units pF pF VCC Conditions 5.0V, VIN 0V 0V Control Pin Input Capacitance Input/Output Capacitance “OFF State” 25qC, f VCC, OE 5.0V, VIN 1 MHz, Capacitance is characterized but not tested. AC Loading and Waveforms Note: Input driven by 50: source terminated in 50: Note: CL includes load and stray capacitance Note: Input PRR 1.0 MHz, tW 500 ns FIGURE 1. AC Test Circuit FIGURE 2. AC Waveforms www.fairchildsemi.com 4 FST162861 20-Bit Bus Switch with 25: Series Resistors in Outputs Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Technology Description The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its 74LVX3L384(FST3384) bus switch product. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com
FST162861
1. 物料型号: - FST162861MTD(48引脚TSSOP封装) - FST162861MTDX_NL(无铅48引脚TSSOP封装)

2. 器件简介: - FST162861是一款20位的高速CMOS TTL兼容总线开关,具有低导通电阻和最小传播延迟。它允许两个端口之间的低阻抗连接,并且具有25欧姆的等效串联电阻,以减少信号反射噪声,无需外部终止电阻。

3. 引脚分配: - OE1, OE2:总线开关使能 - 1A, 2A:总线A - 1B, 2B:总线B

4. 参数特性: - 供电电压(Vcc):-0.5V至+7.0V - DC开关电压(Vs):-0.5V至+7.0V - DC输入电压(VN):-0.5V至+7.0V - DC输入二极管电流(x):VIN<0V时为-50mA - DC输出低电流:128mA - DC Vcc/GND电流:±100mA - 存储温度范围(TSTG):-65°C至+150°C

5. 功能详解: - 当OE为低电平时,开关打开,Port 1A连接到Port 1B;当OE2为低电平时,Port 2A连接到Port 2B;当OE为高电平时,A和B端口之间呈现高阻抗状态。

6. 应用信息: - 该器件适用于需要高速CMOS TTL兼容总线切换的应用场合,特别是在需要减少信号反射噪声和避免额外接地反弹噪声的场合。

7. 封装信息: - 48引脚薄型收缩型小外形封装(TSSOP),符合JEDEC MO-153标准,宽度为6.1mm。
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