FXL2SD106

FXL2SD106 — Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing June 2008 FXL2SD106 Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing Features ■ Bi-directional interface between two levels from 1.1V ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ General Description The FXL2SD106 is a configurable dual-voltage-supply translator designed for both uni-directional and bidirectional voltage translation between two logic levels. The device allows translation between voltages as high as 3.6V to as low as 1.1V. The A port tracks the VCCA level, and the B port tracks the VCCB level. This allows for bi-directional voltage translation over a variety of voltage levels: 1.2V, 1.5V, 1.8V, 2.5V and 3.3V. The FXL2SD106 is specifically designed as a translator to interface with the SDIO standard. I/O capacitance is managed to meet the SD maximum capacitance specification. The B side ESD performance allows interface as an external card and the part can handle 80 Mbps throughput when translating between 1.8V and 2.5V. The device remains in 3-state until both VCCs reach active levels allowing either VCC to be powered-up first. Internal power down control circuits place the device in 3-state if either VCC is removed. The OE input, when low, disables both the A and B ports by placing them in a 3-state condition. The FXL2SD106 is designed so that both control pins (OE and CLK IN) are supplied by VCCA. The device senses an input signal on A or B port automatically. The input signal is transferred to the other port. to 3.6V Fully configurable: Inputs and outputs track VCC level Non-preferential power-up; either VCC may be powered-up first Outputs remain in 3-state until active VCC level is reached Outputs switch to 3-state if either VCC is at GND. Power off protection Bushold on data inputs eliminates the need for SDIO pull-up resistors Control input (OE and CLK IN) are referenced to VCCA voltage Packaged in 16-terminal DQFN (2.5mm x 3.5mm) Direction control not needed 80 Mbps throughput when translating between 1.8V and 2.5V ESD protection exceeds: – 12kV HBM (B port I/O to GND) (per JESD22-A114 & Mil Std 883e 3015.7) – 8kV HBM (A port I/O to GND) (per JESD22-A114 & Mil Std 883e 3015.7) – 1kV CDM (per ESD STM 5.3) Ordering Information Order Number FXL2SD106BQX Package Number MLP16E Package Description 16-Terminal Depopulated Quad Very-Thin Flat Pack, No Leads (DQFN), JEDEC MO-241, 2.5mm x 3.5mm All packages are lead free per JEDEC: J-STD-020B standard. ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 www.fairchildsemi.com FXL2SD106 — Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing Connection Diagram VCCA VCCB 1 16 15 14 13 12 11 10 8 9 Functional Diagram VCCA VCCB CLK IN 2 CMD A 3 A0 4 A1 5 A2 6 A3 7 CLK OUT CMD B B0 B1 B2 B3 OE CMD A CMD B A0–A3 B0–B3 OE GND CLK IN CLK OUT Pin Description Number 1 2 3 4–7 8 9 10–13 14 15 16 Name VCCA CLK IN CMD A A0–A3 OE GND B3–B0 CMD B CLK OUT VCCB Description A Side Power Supply A Side Input A Side Inputs or 3-State Outputs Output Enable Input B Side Inputs or 3-State Outputs 3-State Output B Side Power Supply Function Table Control OE L H 3-State Normal Operation Outputs H = HIGH Logic Level L = LOW Logic Level Power-Up/Power-Down Sequencing FXL translators offer an advantage in that either Vcc may be powered up first. This benefit derives from the chip design. When either VCC is at 0 volts, outputs are in a high-impedance state. The control input (OE) is designed to track the VccA supply. A pull-down resistor tying OE to GND should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power-up/power-down. The size of the pull-down resistor is based upon the current-sinking capability of the device driving the OE pin. The recommended power-up sequence is the following: 1. Apply power to the first VCC. 2. Apply power to the second VCC. 3. Drive the OE input high to enable the device. The recommended power-down sequence is the following: 1. Drive OE input low to disable the device. 2. Remove power from either VCC. 3. Remove power from other VCC. ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 www.fairchildsemi.com 2 FXL2SD106 — Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCCA, VCCB VI Supply Voltage Parameter DC Input Voltage I/O Port A I/O Port B Control Inputs (OE, CLK IN) Output Voltage(1) Outputs 3-STATE Outputs Active (An, CMD A) Outputs Active (Bn, CMD B, CLK OUT) DC Input Diode Current @ VI < 0V DC Output Diode Current @ VO < 0V VO > VCC DC Output Source/Sink Current DC VCC or Ground Current per Supply Pin Storage Temperature Range Rating –0.5V to +4.6V –0.5V to +4.6V –0.5V to +4.6V –0.5V to +4.6V –0.5V to +4.6V –0.5V to VCCA + 0.5V –0.5V to VCCB + 0.5V –50mA –50mA +50mA –50mA / +50mA ±100mA –65°C to +150°C VO IIK IOK IOH / IOL ICC TSTG Note: 1. IO Absolute Maximum Rating must be observed. Recommended Operating Conditions(2) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCCA or VCCB Power Supply Operating Parameter Input Voltage Port A Port B Control Inputs (OE, CLK IN) Dynamic Output Current in IOH/IOL with VCC @ 3.0V to 3.6V 2.3V to 2.7V 1.65V to 1.95V 1.4V to 1.65V 1.1V to 1.4V Static Output Current IOH/IOL with VCC @ 1.1V to 3.6V Rating 1.1V to 3.6V 0.0V to 3.6V 0.0V to 3.6V 0.0V to VCCA ±18.0mA ±11.8mA ±7.4mA ±5.0mA ±2.6mA ±20.0µA –40°C to +85°C 10ns/V TA ∆t / ∆V Free Air Operating Temperature Maximum Input Edge Rate VCCA/B = 1.1V to 3.6V Note: 2. All unused inputs and I/O pins must be held at VCCI or GND. ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 www.fairchildsemi.com 3 FXL2SD106 — Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing DC Electrical Characteristics (TA = –40°C to +85°C) Symbol VIH Parameter High Level Input Voltage VCCA (V) 1.4–3.6 1.1–1.4 1.1–3.6 1.1–3.6 VCCB (V) 1.1–3.6 1.1–3.6 1.4–3.6 1.1–1.4 1.1–3.6 1.1–3.6 1.4–3.6 1.1–1.4 1.1–3.6 1.1–3.6 1.65–3.6 1.1–1.4 1.1–3.6 1.1–3.6 1.65–3.6 1.1–1.4 3.6 2.7 1.95 1.6 1.4 3.6 2.7 1.95 1.6 1.4 3.6 3.6 0 3.6 Conditions Data inputs An, CMD A, Control inputs CLK IN, OE Data inputs Bn, CMD B Min. 0.6 x VCCA 0.9 x VCCA 0.6 x VCCB 0.9 x VCCB Typ. Max. Units V VIL Low Level Input Voltage 1.4–3.6 1.1 –1.4 1.1–3.6 1.1–3.6 Data inputs An, CMD A, Control inputs CLK IN, OE Data inputs Bn, CMD B 0.35 x VCCA 0.1 x VCCA 0.35 x VCCB 0.1 x VCCB 0.75 x VCCA 0.8 0.75 x VCCB 0.8 0.2 x VCCA 0.3 0.2 x VCCB 0.3 450 300 200 120 80 V VOH (3) High Level Output Voltage 1.65–3.6 1.1–1.4 1.1–3.6 1.1–3.6 Data outputs An, CMD A, IHOLD = –20µA Data outputs Bn, CMD B, IHOLD = –20µA Data outputs An, CMD A, IHOLD = 20µA Data outputs Bn, CMD B, IHOLD = 20µA Data inputs An, CMD A, Bn, CMD B V VOL(3) Low Level Output Voltage 1.65–3.6 1.1–1.4 1.1–3.6 1.1–3.6 V II(ODH)(4) Bushold Input Overdrive High Current 3.6 2.7 1.95 1.6 1.4 µA II(ODL) (5) Bushold Input Overdrive Low Current 3.6 2.7 1.95 1.6 1.4 Data inputs An, CMD A, Bn, CMD B -450 -300 -200 -120 -80 µA II IOFF Input Leakage Current Power Off Leakage Current 1.1–3.6 0 3.6 3.6 Control inputs OE, CLK IN, VI = VCCA or GND An, CMD A, VO = 0V to 3.6V Bn, CMD B, CLK OUT, VO = 0V to 3.6V An, CMD A, Bn, CMD B, CLK OUT, VO = 0V or 3.6V, OE = VIL An, CMD A, VO = 0V or 3.6V, OE = Don’t Care Bn, CMD B, CLK OUT, VO = 0V or 3.6V, OE = Don’t Care VI = VCCI or GND, IO = 0 ±1.0 ±2.0 ±2.0 ±2.0 µA µA IOZ(6) 3-State Output Leakage µA 3.6 0 0 3.6 ±2.0 ±2.0 ICCA/B(7)(8) Quiescent Supply Current Quiescent Supply Current 1.1–3.6 1.1–3.6 5.0 µA ICCZ(7) 1.1–3.6 1.1–3.6 VI = VCCI or GND, IO = 0, OE = VIL 5.0 µA ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 www.fairchildsemi.com 4 FXL2SD106 — Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing DC Electrical Characteristics (TA = –40°C to +85°C) (Continued) Symbol ICCA(7) ICCB(7) Parameter Quiescent Supply Current Quiescent Supply Current VCCA (V) 0 1.1–3.6 1.1–3.6 0 VCCB (V) 1.1–3.6 0 0 1.1–3.6 Conditions VI = VCCB or GND; IO = 0 VI = VCCA or GND; IO = 0 VI = VCCB or GND; IO = 0 VI = VCCA or GND; IO = 0 Min. Typ. Max. -2.0 2.0 -2.0 2.0 Units µA µA Notes: 3. This is the output voltage for static conditions. Dynamic drive specifications are given in “Dynamic Output Electrical Characteristics.” 4. An external driver must source at least the specified current to switch LOW-to-HIGH. 5. An external driver must source at least the specified current to switch HIGH-to-LOW. 6. “Don’t Care” indicates any valid logic level. 7. VCCI is the VCC associated with the input side. 8. Reflects current per supply, VCCA or VCCB. Dynamic Output Electrical Characteristics(9) A Port (An, CMD A) Output Load: CL = 15pF, RL ≥ 1MΩ (CI/O = 5pF) TA = -40°C to +85°C, VCCA = 3.0V to 3.6V Symbol trise (10) 2.3V to 2.7V Typ. Max. 3.5 3.5 -11.8 +11.8 1.65V to 1.95V Typ. Max. 4.0 4.0 -7.4 +7.4 1.4V to 1.6V Typ. Max. 5.0 5.0 -5.0 +5.0 1.1V to 1.3V Typ. 7.5 7.5 -2.6 +2.6 Units ns ns mA mA Parameter Output Rise Time A port Output Fall Time A port Dynamic Output Current High Dynamic Output Current Low Typ. Max. 3.0 3.0 tfall(11) IOHD(10) IOLD(11) -18.0 +18.0 B Port (Bn, CMD B, CLK OUT) Output Load: CL = 15pF, RL ≥ 1MΩ (CI/O = 15pF) TA = -40°C to +85°C, VCCB = 3.0V to 3.6V Symbol trise (10) 2.3V to 2.7V Typ. Max. 3.5 3.5 -11.8 +11.8 1.65V to 1.95V Typ. Max. 4.0 4.0 -7.4 +7.4 1.4V to 1.6V Typ. Max. 5.0 5.0 -5.0 +5.0 1.1V to 1.3V Typ. 7.5 7.5 -2.6 +2.6 Units ns ns mA mA Parameter Output Rise Time A port Output Fall Time A port Dynamic Output Current High Dynamic Output Current Low Typ. Max. 3.0 3.0 tfall(11) IOHD(10) IOLD(11) -18.0 +18.0 Notes: 9. Dynamic Output Characteristics are guaranteed but not tested. 10. See Figure 5. 11. See Figure 6. ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 www.fairchildsemi.com 5 FXL2SD106 — Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing AC Characteristics VCCA = 3.0V to 3.6V TA = -40°C to +85°C, VCCB = 3.0V–3.6V Symbol tPLH, tPHL tPLH, tPHL tPZL, tPZH tskew (12) 2.3V–2.7V Min. 0.3 0.2 1.65V–1.95V Min. 0.5 0.3 1.4V–1.6V Min. 0.6 0.5 1.1V–1.3V Typ. 22.0 15.0 15.0 1.7 1.0 Parameter A to B B to A CLK IN to CLK OUT OE to A, OE to B A Port, B Port Min. 0.2 0.2 Max. 3.5 3.5 3.0 1.7 0.5 Max. 3.9 3.8 3.5 1.7 0.5 Max. 5.4 5.0 4.5 1.7 0.5 Max. 6.8 6.0 6.0 1.7 1.0 Units ns ns ns µs ns VCCA = 2.3V to 2.7V TA = -40°C to +85°C, VCCB = 3.0V–3.6V Symbol tPLH, tPHL tPLH, tPHL tPZL, tPZH tskew (12) 2.3V–2.7V Min. 0.4 0.4 1.65V–1.95V Min. 0.5 0.5 1.4V–1.6V Min. 0.8 0.5 1.1V–1.3V Typ. 22.0 15.0 15.0 1.7 1.0 Parameter A to B B to A CLK IN to CLK OUT OE to A, OE to B A Port, B Port Min. 0.2 0.3 Max. 3.8 3.9 3.5 1.7 0.5 Max. 4.2 4.2 4.0 1.7 0.5 Max. 5.6 5.5 4.5 1.7 0.5 Max. 6.9 6.5 6.5 1.7 1.0 Units ns ns ns µs ns VCCA = 1.65V to 1.95V TA = -40°C to +85°C, VCCB = 3.0V–3.6V Symbol tPLH, tPHL tPLH, tPHL tPZL, tPZH tskew(12) 2.3V–2.7V Min. 0.5 0.5 1.65V–1.95V Min. 0.8 0.8 1.4V–1.6V Min. 0.9 1.0 1.1V–1.3V Typ. 22.0 15.0 15.0 1.7 1.0 Parameter A to B B to A CLK IN to CLK OUT OE to A, OE to B A Port, B Port Min. 0.3 0.5 Max. 5.0 5.4 4.5 1.7 0.5 Max. 5.5 5.6 4.5 1.7 0.5 Max. 6.7 6.7 6.3 1.7 0.5 Max. 7.5 7.0 6.7 1.7 1.0 Units ns ns ns µs ns VCCA = 1.4V to 1.6V TA = -40°C to +85°C, VCCB = 3.0V–3.6V Symbol tPLH, tPHL tPLH, tPHL tPZL, tPZH tskew (12) 2.3V–2.7V Min. 0.5 0.8 1.65V–1.95V Min. 1.0 0.9 1.4V–1.6V Min. 1.0 1.0 1.1V–1.3V Typ. 22.0 15.0 15.0 1.7 1.0 Parameter A to B B to A CLK IN to CLK OUT OE to A, OE to B A Port, B Port Min. 0.5 0.6 Max. 6.0 6.8 6.0 1.7 1.0 Max. 6.5 6.9 6.5 1.7 1.0 Max. 7.0 7.5 6.7 1.7 1.0 Max. 8.5 8.5 8.5 1.7 1.0 Units ns ns ns µs ns Note: 12. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (An, CMD A or Bn, CMD B) and switching with the same polarity (Low-to-High or High-to-Low). See Figure 8. ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 www.fairchildsemi.com 6 FXL2SD106 — Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing Max Data Rate(13)(14) TA = -40°C to +85°C, VCCB = 3.0V to 3.6V 2.3V to 2.7V 1.65V to 1.95V 1.4V to 1.6V 1.1V to 1.3V VCCA VCCA = 3.0V to 3.6V VCCA = 2.3V to 2.7V VCCA =1.65V to 1.95V VCCA = 1.4V to 1.6V VCCA = 1.1V to 1.3V Min. 100 100 80 60 Min. 100 100 80 60 Min. 80 80 60 40 Min. 60 60 40 40 Typ. 20 20 20 20 Units Mbps Mbps Mbps Mbps Typ. 20 Typ. 20 Typ. 20 Typ. 20 Typ. 20 Mbps Note: 13. Max Data Rate is guaranteed but not tested. 14. Max Data Rate is specified in megabits per second. See Figure 7. It is equivalent to two times the F-toggle frequency, specified in megahertz. For example, 100 Mbps is equivalent to 50 MHz. Capacitance TA = +25°C Symbol Cin Ci/o Parameter Input Capacitance, Control pin (OE, CLK IN) Input/Output Capacitance An, CMD A Bn, CMD B, CLK OUT Conditions VccA = VccB = GND VccA = VccB = 3.3V, OE = VccA VccA = VccB = 3.3V, Vi = 0V or Vcc, f = 10MHz Typical 4 5 6 25 Units pF pF Cpd Power Dissipation Capacitance pF ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 www.fairchildsemi.com 7 FXL2SD106 — Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing VCC TEST SIGNAL DUT C1 R1 Test tPLH, tPHL tPZL tPZH Input Signal Data Pulses 0V VCCI Output Enable Control VCCA Low to High Switch Low to High Switch Figure 1. AC Test Circuit AC Load Table VCCO 1.2V ± 0.1V 1.5V ± 0.1V 1.8V ± 0.15V 2.5V ± 0.2V 3.3 ± 0.3V Cl 15pF 15pF 15pF 15pF 15pF Rl 1MΩ 1MΩ 1MΩ 1MΩ 1MΩ ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 www.fairchildsemi.com 8 FXL2SD106 — Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing DATA IN tpxx DATA OUT Input tR = tF = 2.0ns, 10% to 90% Vmi tpxx Vmo VCCI GND OUTPUT CONTROL tPZL VCCO DATA OUT VY VOL Vmi VCCA GND Input tR = tF = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only Input tR = tF = 2.0ns, 10% to 90% Input tR = tF = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only Figure 2. Waveform for Inverting and Non-inverting Functions Figure 3. 3-STATE Output Low Enable Time for Low Voltage Logic Symbol OUTPUT CONTROL tPZH DATA OUT Vx VOH Vmi VCCA GND Vcc VCCI / 2 VCCO / 2 0.9 x VCCO 0.1 x VCCO Vmi(15) Vmo VX VY Input tR = tF = 2.0ns, 10% to 90% Input tR = tF = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only Note: 15. VCCI = VCCA for control pin OE or Vmi = (VCCA / 2). Figure 4. 3-STATE Output High Enable Time for Low Voltage Logic ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 www.fairchildsemi.com 9 FXL2SD106 — Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing trise VOH 80% x VCCO VOH 80% x VCCO VOUT tfall VOUT 20% x VCCO VOL Time IOHD ≈ (CL +CI/O) x ∆VOUT (20% – 80%) x VCCO = (CL +CI/O) x ∆t tRISE IOLD ≈ (CL +CI/O) x 20% x VCCO VOL Time ∆VOUT (80% – 20%) x VCCO = (CL +CI/O) x tFALL ∆t Figure 5. Active Output Rise Time and Dynamic Output Current High Figure 6. Active Output Fall Time and Dynamic Output Current Low tW DATA IN VCCI VCCI/2 Max. data rate, f = 1/tW VCCI/2 GND DATA OUTPUT tskew DATA OUTPUT VCCO Vmo Vmo GND tskew VCCO Vmo Vmo GND Figure 7. Maximum Data Rate tskew = (tpHLmax – tpHLmin) or (tpLHmax – tpLHmin) Figure 8. Output Skew Time ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 www.fairchildsemi.com 10 FXL2SD106 — Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing Tape and Reel Specification Tape Format for DQFN 10 Package Designator BQX Tape Section Leader (Start End) Carrier Trailer (Hub End) Number Cavities 125 (typ) 2500/3000 75 (typ) Cavity Status Empty Filled Empty Cover Tape Status Sealed Sealed Sealed Tape Dimensions millimeters ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 www.fairchildsemi.com 11 FXL2SD106 — Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing Reel Dimensions inches (millimeters) Tape Size 12mm A 13.0 (330) B 0.059 (1.50) C 0.512 (13.00) D 0.795 (20.20) N 7.008 (178) W1 0.488 (12.4) W2 0.724 (18.4) ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 www.fairchildsemi.com 12 FXL2SD106 — Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing Physical Dimensions Figure 9. 6-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241 2.5mm x 3.5mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 www.fairchildsemi.com 13 FXL2SD106 — Low Voltage Dual Supply 6-Bit SD Interface Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. ACEx Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ ® EcoSPARK EfficentMax™ EZSWITCH™ * ™ ® ® Fairchild ® Fairchild Semiconductor FACT Quiet Series™ ® FACT ® FAST FastvCore™ ®* FlashWriter ® ® FPS™ F-PFS™ ® FRFET SM Global Power Resource Green FPS™ Green FPS™ e-Series™ GTO™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ MotionMax™ Motion-SPM™ ® OPTOLOGIC ® OPTOPLANAR ® PDP SPM™ Power-SPM™ ® PowerTrench Programmable Active Droop™ ® QFET QS™ Quiet Series™ RapidConfigure™ Saving our world, 1mW at a time™ SmartMax™ SMART START™ ® SPM STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SupreMOS™ SyncFET™ ® The Power Franchise ® TinyBoost™ TinyBuck™ ® TinyLogic TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ µSerDes™ UHC Ultra FRFET™ UniFET™ VCX™ VisualMax™ ® * EZSWITCH™ and FlashWriter are trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative / In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. This datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I34 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. First Production No Identification Needed Obsolete Full Production Not In Production ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 www.fairchildsemi.com 14