GTLP6C817

GTLP6C817 Low Drive GTLP-to-LVTTL 1:6 Clock Driver June 1999 Revised August 1999 GTLP6C817 Low Drive GTLP-to-LVTTL 1:6 Clock Driver General Description The GTLP6C817 is a low drive clock driver that provides TTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing ( VCC ESD Rating Storage Temperature (TSTG) −50 mA +50 mA > 2000V −65°C to +150°C −50 mA 80 mA −24 mA 24 mA −0.5V to +7.0V −0.5V to +7.0V −0.5V to +7.0V −0.5V to +7.0V Recommended Operating Conditions (Note 3) Supply Voltage VCC VCCT Bus Termination Voltage (VTT) GTLP VREF Input Voltage (VI) on INA-Port and Control Pins HIGH Level Output Current (IOH) OA-Port LOW Level Output Current (IOL) OA-Port OB-Port Operating Temperature (TA) +12 mA +40 mA −40°C to +85°C −12 mA 0.0V to 5.5V 1.47V to 1.53V 0.98V to 1.02V 4.75V to 5.25V 3.15V to 3.45V Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 2: Io Absolute Maximum Rating must be observed. Note 3: Unused input must be held HIGH or LOW. 3 www.fairchildsemi.com GTLP6C817 DC Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL VREF (Note 5) VTT (Note 5) VIK VOH OAn-Port GTLPIN Others GTLPIN Others GTLP GTL GTLP GTL VCC = 4.75V VCCT = 3.15V VCC = 4.75V VCCT = 3.15V VOL OAn-Port VCC = 4.75V VCCT = 3.15V VOL II OBn-Port TTLIN/ Control Pins GTLPIN IOFF IOZH IOZL IPU/PD ICC (5V) VCC = 4.75V VCCT = 3.15V VCC = 5.25V VCCT = 3.45V VCC = 5.25V VCCT = 3.45V TTLIN, OAn-Port, Control Pins VCC = 0 GTLPIN, OBn-Port OAn-Port OBn-Port OAn-Port OBn-Port All Ports OAn or OBn Ports VCCT = 0 VCC = 5.25V VCCT = 3.45V VCC = 5.25V VCCT = 3.45V VCC = 5.25V VCCT = 3.45V II = −18 mA IOH = −100 µA IOH = −6 mA IOH = −12 mA IOL = 100 µA IOL = 6 mA IOL = 12 mA IOL = 100 µA IOL = 40 mA VI = 5.25V VI = 0V VI = VTT VI = 0 VI or VO = 0V to 5.25V VI or VO = 0 to VTT VO = 5.25V VO = 1.5V VO = 0 VO = 0 VCC− 0.2 2.4 2.2 0.2 0.4 0.5 0.2 0.5 5 −5 5 −5 30 30 5 5 −5 30 10 10 10 45 45 µA mA V µA µA µA µA µA µA V V 1.0 0.8 1.5 1.2 −1.2 Test Conditions Min VREF + 0.05 2.0 0.0 VREF − 0.05 0.8 Typ (Note 4) Max VTT Units V V V V V VCC = VCCT = 0 to 1.5V OE = Don’t Care Outputs HIGH Outputs LOW Outputs Disabled VI = VCC or GND ICC (3V) OAn or OBn Ports VCC = 5.25V VCCT = 3.45V VCC = 5.25V VCCT = 3.45V Outputs HIGH, LOW Outputs Disabled VI = VCC or GND ∆ICC CIN COUT TTLIN Control Pins/GTLPIN/TTLIN OAn-Port OBn-Port VI = VCC−2.1 VI = VCC or 0 VI = VCC or 0 VI = VCC or 0 3 3 4 1 3.5 4.5 5 mA pF pF Note 4: All typical values are at VCC = 5.0V VCCT = 3.3V and TA = 25°C. Note 5: GTLP VREF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In addition, VTT and RTERM can be adjusted to accommodate backplane impedances other than 50Ω , within the boundaries of not exceeding the DC Absolute IOL ratings. Similarly VREF can be adjusted to compensate for changes in V TT. www.fairchildsemi.com 4 GTLP6C817 AC Electrical Characteristics Over recommended range of supply voltage and operating free air temperature. VREF = 1.0V (unless otherwise noted). CL = 30 pF for OBn-Port and CL = 50 pF for OAn-Port. Typ Symbol tPLH tPHL tPLH tPHL tRISE tFALL tRISE tFALL tPZH, tPZL tPLZ, tPHZ tPLH tPHL Note 6: All typical values are at VCC = 5.0V and TA = 25°C. From (Input) TTLIN To (Output) OBn Min (Note 6) 2.3 1.5 Max 4.7 Units ns 4.6 4.8 ns 1.6 Transition Time, OB Outputs (20% to 80%) Transition Time, OB outputs (20% to 80%) Transition Time, OA outputs (10% to 90%) Transition Time, OA outputs (10% to 90%) OEA OAn 2.4 2.0 GTLPIN OAn 3.1 2.8 1.7 2.1 2.7 2.2 6.5 ns 6.5 6.6 ns 6.0 4.7 ns ns ns ns OEB OBn 2.4 Extended Electrical Characteristics Over recommended ranges of supply voltage and operating free-air temperature VREF = 1.0V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol tOSLH tOSHL tPS tPV(HL) tOSLH tOSHL tOST tPS tPV (Note 8) (Note 8) (Note 9) (Note 10) (Note 11) (Note 8) (Note 8) (Note 8) (Note 9) (Note 10) From (Input) A A A A B B B B B To (Output) B B B B A A A A A .12 .12 .6 0.5 Min Typ (Note 7) .05 .05 0.5 Max .4 .4 1.0 .7 .5 .5 1.0 1.0 1.2 ns ns ns ns ns ns Unit ns Note 7: All typical values are at VCC = 5.0V and TA = 25°C. Note 8: tOSHL/tOSLH and tOST - Output-to-Output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 9: tPS - Pin or Transition skew is defined as the difference between the LOW-to-HIGH transition and the HIGH-to-LOW transition on the same pin. The parameter is measured across all the outputs of the same chip is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 10: tPV - Part-to-Part skew is defined as the absolute value of the difference between the actual propagation design for all outputs from device-todevice. The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP output could vary on the backplane due to the loading and impedance seen by the device. Note 11: Due to the open drain structure on GTLP outputs, tOST and tPV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the VTT and RT values in the actual application. 5 www.fairchildsemi.com GTLP6C817 Test Circuit and Timing Waveforms Test Circuit for A Outputs Test Circuit for B Outputs Note A: CL includes probes and jig capacitance. Note A: CL includes probes and jig capacitance. Note B: For B Port CL = 30 pF is used for worst case. Voltage Waveform - Propagation Delay Times Voltage Waveform - Enable and Disable Times Output Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the control output Output Waveforms 2 is for an output with internal conditions such that the output is HIGH except when disabled by the control output Input and Measure Conditions A or LVTTL Pins VinHIGH VinLOW VM VX VY VCC 0.0 VCC/2 VOL + 0.3V VOH + 0.3V B or GTLP Pins 1.5 0.0 1.0 N/A N/A All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns, ZO = 50Ω. The outputs are measured one at a time with one transition per measurement. www.fairchildsemi.com 6 GTLP6C817 Low Drive GTLP-to-LVTTL 1:6 Clock Driver Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com