IRFP140

IGNS DES W E T OR N DUC ED F TE PRO D N MME BSTITU ECOSheet SU R 0N Data January 2002 T NO IBLE IRFP14 S S PO 31A, 100V, 0.077 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17421. Ordering Information PART NUMBER PACKAGE IRFP140 Features • 31A, 100V • rDS(ON) = 0.077Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol BRAND D IRFP140 TO-247 IRFP140 NOTE: When ordering, include the entire part number. G S Packaging JEDEC STYLE TO-247 SOURCE DRAIN GATE DRAIN (FLANGE) ©2002 Fairchild Semiconductor Corporation IRFP140 Rev. B IRFP140 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFP140 100 100 31 22 120 ±20 180 1.2 100 -55 to 175 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER BVDSS VGS = 0V, ID = 250µA (Figure 10) 100 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V - - 25 µA - - 250 µA 31 - - A Zero Gate Voltage Drain Current SYMBOL IDSS TEST CONDITIONS VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC On-State Drain Current (Note 2) Gate to Source Leakage Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V VGS = ±20V - - ±100 nA VGS = 10V, ID = 19A (Figures 8, 9) - 0.055 0.077 Ω 9.3 14 - S - 15 23 ns - 72 110 ns - 40 60 ns VDS ≥ 50V, ID = 19A (Figure 12) VDD = 50V, ID ≈ 28A, RGS = 9.1Ω, RL = 1.7Ω, VGS = 10V MOSFET Switching Times are Essentially Independent of Operating Temperature tf Qg(TOT) Qgs - 50 75 ns VGS = 10V, ID ≈ 27A, VDS = 0.8 x Rated BVDSS, IG(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature - 38 59 nC - 10 - nC - 21 - nC VGS = 0V, VDS ≈ 25V, f = 1.0MHz (Figure 11) - 1275 - pF Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS - 550 - pF Reverse Transfer Capacitance CRSS - 160 - pF - 5.0 - nH - 12.5 - nH - - 0.83 oC/W - - 30 oC/W Internal Drain Inductance LD Measured between the Contact Screw on Header that is Closer to Source and Gate Pins and Center of Die Internal Source Inductance LS Measured from the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA ©2002 Fairchild Semiconductor Corporation Free Air Operation IRFP140 Rev. B IRFP140 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode D MIN TYP MAX UNITS - - 31 A - - 120 A - - 2.5 V 70 150 300 ns 0.44 0.91 1.9 µC G S Source to Drain Diode Voltage (Note 2) VSD Reverse Recovery Time trr Reverse Recovered Charge QRR TJ = 25oC, ISD = 31A, VGS = 0V (Figure 13) TJ = 25oC, ISD = 28A, dISD/dt = 100A/µs TJ = 25oC, ISD = 28A, dISD/dt = 100A/µs NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 25V, starting TJ = 25oC, L = 160µH, RG = 50Ω, peak IAS = 31A. Typical Performance Curves Unless Otherwise Specified 40 1.0 ID , DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 0.2 24 16 8 0 0 25 0 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 25 175 50 75 125 100 175 150 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE ZθJC , TRANSIENT THERMAL IMPEDANCE 32 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 10 1 0.5 0.1 10-2 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 t2 SINGLE PULSE 10-3 10-5 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC 10-4 10-3 10-2 0.1 1 10 t1 , RECTANGULAR PULSE DURATION (s) FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE ©2002 Fairchild Semiconductor Corporation IRFP140 Rev. B IRFP140 Typical Performance Curves (Continued) 50 OPERATION IN THIS REGION IS LIMITED BY rDS(ON) ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 103 Unless Otherwise Specified 10µs 102 100µs 1ms 10 10ms TC = 25oC TJ = MAX RATED SINGLE PULSE DC 40 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 30 VGS = 6V 20 VGS = 5V 10 VGS = 4V 1 102 1 0 103 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 102 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 7.0V VGS = 10V 40 VGS = 8V 30 10 20 30 40 VDS , DRAIN TO SOURCE VOLTAGE (V) 50 FIGURE 5. OUTPUT CHARACTERISTICS ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 50 VGS = 7V VGS = 10V VGS = 8V VGS = 6V 20 VGS = 5V 10 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS ≥ 50V 10 TJ = 25oC TJ = 175oC 1 VGS = 4V 0 0 1 2 3 4 VDS , DRAIN TO SOURCE VOLTAGE (V) 5 0.1 0 FIGURE 6. SATURATION CHARACTERISTICS 3.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VOLTAGE PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0.6 VGS = 10V 0.4 0.2 VGS = 20V 0 0 25 50 75 ID , DRAIN CURRENT (A) 100 125 NOTE: Heating effect of 2µs pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT ©2002 Fairchild Semiconductor Corporation 10 FIGURE 7. TRANSFER CHARACTERISTICS 0.8 ON RESISTANCE (Ω) rDS(ON), DRAIN TO SOURCE 1.0 2 4 6 8 VGS , GATE TO SOURCE VOLTAGE (V) 2.4 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID = 19A, VGS = 10V 1.8 1.2 0.6 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRFP140 Rev. B IRFP140 Typical Performance Curves (Continued) 3000 ID = 250µA 1.15 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 Unless Otherwise Specified 1.05 0.95 0.85 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD 2400 COSS ≈ CDS + CGD 1800 CISS 1200 COSS 600 CRSS 0.75 -60 -40 -20 0 20 40 60 0 80 100 120 140 160 180 0 2 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE TJ = 25oC 12 TJ = 175oC 8 4 0 20 50 100 103 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS ≥ 50V 16 10 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE ISD, SOURCE TO DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) 20 5 VDS , DRAIN TO SOURCE VOLTAGE (V) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 102 TJ = 175oC 10 TJ = 25oC 1 0 10 20 30 ID , DRAIN CURRENT (A) 40 50 0 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 0.6 1.2 1.8 2.4 VSD , SOURCE TO DRAIN VOLTAGE (V) 3.0 FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE VGS, GATE TO SOURCE VOLTAGE (V) 20 ID = 34A 16 VDS = 20V 12 VDS = 50V VDS = 80V 8 4 0 0 12 24 36 48 60 Qg, GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE ©2002 Fairchild Semiconductor Corporation IRFP140 Rev. B IRFP140 Test Circuits and Waveforms VDS BVDSS tP L VDS IAS VARY tP TO OBTAIN VDD + RG REQUIRED PEAK IAS - VGS VDD DUT tP 0V 0 IAS 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tr VDS RL 90% + RG - VGS 0 VGS 0.2µF 50% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd D VDS DUT G IG(REF) 0 S IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT ©2002 Fairchild Semiconductor Corporation VGS Qgs 0.3µF 0 50% PULSE WIDTH 10% FIGURE 17. SWITCHING TIME TEST CIRCUIT 12V BATTERY 10% 90% DUT CURRENT REGULATOR 90% 10% 0 VDD tf IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRFP140 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST  FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench  QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER  SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET  VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4