IRLU110A

$GYDQFHG 3RZHU 026)(7 FEATURES ♦ Avalanche Rugged Technology ♦ Rugged Gate Oxide Technology ♦ Lower Input Capacitance ♦ Improved Gate Charge ♦ Extended Safe Operating Area ♦ Lower Leakage Current: 10µA (Max.) @ VDS = 100V ♦ Lower RDS(ON): 0.336Ω (Typ.) IRLR/U110A BVDSS = 100 V RDS(on) = 0.44Ω ID = 4.7 A D-PAK 2 1 3 1 I-PAK 2 3 1. Gate 2. Drain 3. Source Absolute Maximum Ratings Symbol VDSS ID IDM VGS EAS IAR EAR dv/dt PD Characteristic Drain-to-Source Voltage Continuous Drain Current (TC=25°C) Continuous Drain Current (TC=100°C) Drain Current-Pulsed Gate-to-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Total Power Dissipation (TA=25°C) * Total Power Dissipation (TC=25°C) Linear Derating Factor TJ , TSTG TL Operating Junction and Storage Temperature Range Maximum Lead Temp. for Soldering Purposes, 1/8 from case for 5-seconds (2) (1) (1) (3) (1) Value 100 4.7 3 16 ±20 58 4.7 2.2 6.5 2.5 22 0.18 - 55 to +150 Units V A A V mJ A mJ V/ns W W W/°C °C 300 Thermal Resistance Symbol RθJC RθJA RθJA Characteristic Junction-to-Case Junction-to-Ambient * Junction-to-Ambient Typ. ---Max. 5.6 50 110 °C/W Units * When mounted on the minimum pad size recommended (PCB Mount). Rev. B ©1999 Fairchild Semiconductor Corporation 1 IRLR/U110A Electrical Characteristics (TC=25°C unless otherwise specified) Symbol BVDSS ∆BV/∆TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd Characteristic Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coeff. Gate Threshold Voltage Gate-Source Leakage , Forward Gate-Source Leakage , Reverse Drain-to-Source Leakage Current Static Drain-Source On-State Resistance Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain ( Miller ) Charge Min. Typ. Max. Units 100 -1.0 -----------------0.1 ------3.2 180 50 20 8 10 17 8 5.5 0.9 3.5 --2.0 100 -100 10 100 0.44 -235 65 25 25 30 45 25 8 --nC ns pF µA Ω Ω V V nA 1&+$11(/ 32:(5 026)(7 Test Condition VGS=0V,ID=250µA V/° C ID=250µA VGS=20V VGS=-20V VDS=100V See Fig 7 VDS=5V,ID=250µA VDS=80V,TC=125°C VGS=5V,ID=2.35A VDS=40V,ID=2.35A (4) (4) VGS=0V,VDS=25V,f =1MHz See Fig 5 VDD=50V,ID=5.6A, RG=12Ω See Fig 13 VDS=80V,VGS=5V, ID=5.6A (4) (5) See Fig 6 & Fig 12 (4) (5) Source-Drain Diode Ratings and Characteristics Symbol IS ISM VSD trr Qrr Characteristic Continuous Source Current Pulsed-Source Current Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge (1) (4) Min. Typ. Max. Units --------85 0.23 4.7 16 1.5 --A V ns µC Test Condition Integral reverse pn-diode in the MOSFET TJ=25°C,IS=4.7A,VGS=0V TJ=25°C,IF=5.6A diF/dt=100A/µs (4) Notes; (1) Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature (2) L=4mH, IAS=4.7A, VDD=25V, RG=27Ω, Starting TJ =25°C (3) ISD ≤ 5.6A, di/dt ≤ 250A/µs, VDD ≤ BVDSS , Starting TJ =25°C (4) Pulse Test: Pulse Width = 250µ s, Duty Cycle ≤ 2% (5) Essentially Independent of Operating Temperature 2 1&+$11(/ 32:(5 026)(7 IRLR/U110A Fig 2. Transfer Characteristics 11 0 Fig 1. Output Characteristics VGS 11 0 Top : ID , Drain Current [A] ID , Drain Current [A] 7.0 V 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V Bottom : 3.0 V 1 0 oC 5 10 0 2 oC 5 @ Nt s: oe 1 V =0 V . GS 2 V =4 V . DS 0 3 2 0 µs P l e T s .5 us et 6 8 1 0 10 0 @ Nt s: oe 1 2 0 µs P l e T s .5 us et 2 T = 2 oC .C 5 1 -1 0 1 -1 0 10 0 11 0 - 5 oC 5 1 -1 0 0 2 4 VDS , Drain-Source Voltage [V] VGS , Gate-Source Voltage [V] Fig 3. On-Resistance vs. Drain Current 08 . Fig 4. Source-Drain Diode Forward Voltage 11 0 Drain-Source On-Resistance 06 . V =5 V GS 04 . IDR , Reverse Drain Current [A] RDS(on) , [ Ω ] 10 0 02 . V =1 V 0 GS @ Nt :T =2 C oe J 5 o 1 0 oC 5 2C 5 1 -1 0 04 . 06 . 08 . 10 . 12 . o @ Nt s: oe 1 V = 0V . GS us et 2 2 0 µs P l e T s .5 14 . 16 . 18 . 20 . 00 . 0 5 D 1 0 1 5 2 0 I , Drain Current [A] VSD , Source-Drain Voltage [V] Fig 5. Capacitance vs. Drain-Source Voltage 30 5 C = C + C (C = so td ) iss gs gd ds h r e C =C +C oss ds gd C =C rss gd C iss 20 1 C oss 10 4 C rss 7 0 @ Nt s: oe 1 V =0 V . GS 2 f =1 M z . H 6 Fig 6. Gate Charge vs. Gate-Source Voltage 20 8 VGS , Gate-Source Voltage [V] Capacitance [pF] V =2 V 0 DS V =5 V 0 DS V =8 V 0 DS 4 2 @Nts: I =56A oe . D 0 0 G 0 10 0 1 0 1 2 4 6 VDS , Drain-Source Voltage [V] Q , Total Gate Charge [nC] 3 IRLR/U110A Fig 7. Breakdown Voltage vs. Temperature 12 . 25 . 1&+$11(/ 32:(5 026)(7 Fig 8. On-Resistance vs. Temperature Drain-Source Breakdown Voltage RDS(on) , (Normalized) Drain-Source On-Resistance 20 . BVDSS , (Normalized) 11 . 15 . 10 . 10 . @Nts: oe 1 V =5V . GS 2 I =28A .D . -0 5 -5 2 0 2 5 5 0 7 5 10 0 15 2 10 5 15 7 09 . @ Nt s: oe 1 V =0 V . GS 2 I = 2 0 µA .D 5 05 . 08 . -5 7 -0 5 -5 2 0 2 5 5 0 7 5 10 0 15 2 10 5 15 7 00 . -5 7 TJ , Junction Temperature [oC] TJ , Junction Temperature [oC] Fig 9. Max. Safe Operating Area 12 0 O ea in i Ti Ae pr t o n h s r a i L m t d b R DS(on) s i ie y Fig 10. Max. Drain Current vs. Case Temperature 5 ID , Drain Current [A] 11 0 1 0 µs 0 1m s 1m 0s ID , Drain Current [A] 4 3 1 0 0 D C @ Nt s: oe 1 T = 2 oC .C 5 2 1 -1 0 2T .J 3 S nl Pl e . ig e us = 1 0 oC 5 1 1 -2 0 0 1 0 11 0 12 0 0 2 5 5 0 c 7 5 10 0 15 2 10 5 VDS , Drain-Source Voltage [V] T , Case Temperature [oC] Thermal Response 101 Fig 11. Thermal Response D=0.5 100 0.2 0.1 0.05 @ Notes : 1. Z J C (t)=5.6 o C/W Max. θ 2. Duty Factor, D=t /t 1 2 Z (t) , 3. TJ M -TC =PD M *Z PDM θJC (t) 0.02 0.01 θJC single pulse t1 t2 10- 1 10- 5 10- 4 10- 3 10- 2 10- 1 100 101 t 1 , Square Wave Pulse Duration [sec] 4 1&+$11(/ 32:(5 026)(7 IRLR/U110A Fig 12. Gate Charge Test Circuit & Waveform Current Regulator 50kΩ 12V 200nF 300nF Same Type as DUT VGS Qg 10V VDS VGS DUT 3mA Qgs Qgd R1 Current Sampling (IG) Resistor R2 Current Sampling (ID) Resistor Charge Fig 13. Resistive Switching Test Circuit & Waveforms RL Vout Vin RG DUT Vin 10V td(on) t on tr td(off) t off tf 10% Vout VDD ( 0.5 rated VDS ) 90% Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms LL VDS Vary tp to obtain required peak ID BVDSS 1 EAS = ---- LL IAS2 -------------------2 BVDSS -- VDD BVDSS IAS C VDD VDD tp ID RG DUT 5V tp ID (t) VDS (t) Time 5 IRLR/U110A Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms 1&+$11(/ 32:(5 026)(7 DUT + VDS -- IS L Driver RG VGS Same Type as DUT VGS VDD dv/dt controlled by RG IS controlled by Duty Factor D VGS ( Driver ) Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current IS ( DUT ) IRM di/dt Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt Vf VDD Body Diode Forward Voltage Drop 6 DPAK Package Dimensions DPAK (FS PKG CODE AA) 6.60 ±0.20 5.34 ±0.30 (0.50) (4.34) (0.50) 0.70 ±0.20 2.30 ±0.10 0.50 ±0.10 0.60 ±0.20 6.10 ±0.20 2.70 ±0.20 9.50 ±0.30 0.91 ±0.10 0.80 ±0.20 MAX0.96 2.30TYP [2.30±0.20] 0.76 ±0.10 2.30TYP [2.30±0.20] 0.89 ±0.10 0.50 ±0.10 1.02 ±0.20 2.30 ±0.20 (0.70) (0.90) (0.10) (3.05) 6.10 ±0.20 9.50 ±0.30 2.70 ±0.20 (2XR0.25) 0.76 ±0.10 Dimensions in Millimeters September 1999, Rev B (1.00) 6.60 ±0.20 (5.34) (5.04) (1.50) MIN0.55 IPAK Package Dimensions IPAK (FS PKG CODE AL) 6.60 ±0.20 5.34 ±0.20 (0.50) (4.34) (0.50) 0.50 ±0.10 2.30 ±0.20 0.60 ±0.20 0.70 ±0.20 0.80 ±0.10 6.10 ±0.20 1.80 ±0.20 MAX0.96 0.76 ±0.10 9.30 ±0.30 2.30TYP [2.30±0.20] 2.30TYP [2.30±0.20] 0.50 ±0.10 Dimensions in Millimeters September 1999, Rev B 16.10 ±0.30 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ DISCLAIMER ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 TinyLogic™ UHC™ VCX™ FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. 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Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.