ISL9N312AD3 / ISL9N312AD3ST
N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs
General Description
Features
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
• Fast switching
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
• rDS(ON) = 0.017Ω (Typ), VGS = 4.5V
Applications
• Qgd (Typ) = 4.5nC
• DC/DC converters
• CISS (Typ) = 1450pF
• rDS(ON) = 0.010Ω (Typ), VGS = 10V
• Qg (Typ) = 13nC, VGS = 5V
D
D
G
G
S
I-PAK
(TO-251AA)
D-PAK
TO-252
(TO-252)
S
G D S
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
30
Units
V
VGS
Gate to Source Voltage
±20
V
Continuous (TC = 25oC, VGS = 10V)
50
A
Continuous (TC = 100oC, VGS = 4.5V)
32
A
Continuous (TC = 25oC, VGS = 10V, RθJA = 52oC/W)
11
A
Drain Current
ID
Pulsed
PD
Power dissipation
Derate above 25oC
TJ, TSTG
Operating and Storage Temperature
Figure 4
A
75
0.5
W
W/oC
o
-55 to 175
C
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case TO-251, TO-252
2
RθJA
Thermal Resistance Junction to Ambient TO-251, TO-252
100
RθJA
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area
52
o
C/W
oC/W
o
C/W
Package Marking and Ordering Information
Device Marking
N312AD
Device
ISL9N312AD3ST
Package
TO-252AA
Reel Size
330mm
Tape Width
16mm
Quantity
2500 units
N312AD
ISL9N312AD3
TO-251AA
Tube
NA
50 units
©2002 Fairchild Semiconductor Corporation
ISL9N312AD3 / ISL9N312AD3ST Rev C
ISL9N312AD3 / ISL9N312AD3ST
June 2002
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
30
-
-
-
V
-
1
-
-
250
µA
VGS = ±20V
-
-
±100
nA
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
VDS = 25V
VGS = 0V
TC = 150o
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
1
-
3
V
ID = 50A, VGS = 10V
-
0.010
0.012
ID = 32A, VGS = 4.5V
-
0.017
0.020
Ω
-
1450
-
-
300
-
pF
-
120
-
pF
nC
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
-
25
38
Qg(5)
Total Gate Charge at 5V
-
13
20
nC
Qg(TH)
Threshold Gate Charge
-
1.5
2.3
nC
Qgs
Gate to Source Gate Charge
VGS = 0V to 5V VDD = 15V
VGS = 0V to 1V ID = 32A
Ig = 1.0mA
Qgd
Gate to Drain “Miller” Charge
Switching Characteristics
VDS = 15V, VGS = 0V,
f = 1MHz
pF
-
4.3
-
nC
-
4.5
-
nC
(VGS = 4.5V)
tON
Turn-On Time
-
-
115
ns
td(ON)
Turn-On Delay Time
-
15
-
ns
tr
Rise Time
td(OFF)
Turn-Off Delay Time
tf
tOFF
-
60
-
ns
-
25
-
ns
Fall Time
-
30
-
ns
Turn-Off Time
-
-
83
ns
Switching Characteristics
VDD = 15V, ID = 11A
VGS = 4.5V, RGS = 11Ω
(VGS = 10V)
tON
Turn-On Time
-
-
57
ns
td(ON)
Turn-On Delay Time
-
8
-
ns
tr
Rise Time
td(OFF)
Turn-Off Delay Time
tf
tOFF
-
30
-
ns
-
45
-
ns
Fall Time
-
30
-
ns
Turn-Off Time
-
-
115
ns
195
-
-
µs
V
VDD = 15V, ID = 11A
VGS = 10V, RGS = 11Ω
Unclamped Inductive Switching
tAV
Avalanche Time
ID = 2.9A, L = 3.0mH
Drain-Source Diode Characteristics
ISD = 32A
-
-
1.25
ISD = 15A
-
-
1.0
V
Reverse Recovery Time
ISD = 32A, dISD/dt = 100A/µs
-
-
20
ns
Reverse Recovered Charge
ISD = 32A, dISD/dt = 100A/µs
-
-
7
nC
VSD
Source to Drain Diode Voltage
trr
QRR
©2002 Fairchild Semiconductor Corporation
ISL9N312AD3 / ISL9N312AD3ST Rev C
ISL9N312AD3 / ISL9N312AD3ST
Electrical Characteristics TC = 25°C unless otherwise noted
TC = 25°C unless otherwise noted
1.2
60
VGS = 10V
ID , DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
40
VGS = 4.5V
20
0
0
0
25
50
75
100
150
125
TC , CASE TEMPERATURE
25
175
50
75
(oC)
100
125
TC , CASE TEMPERATURE
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
150
175
(oC)
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
IDM , PEAK CURRENT (A)
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I = I25
175 - TC
150
VGS = 10V
VGS = 5V
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
30
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation
ISL9N312AD3 / ISL9N312AD3ST Rev C
ISL9N312AD3 / ISL9N312AD3ST
Typical Characteristic
100
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
TJ = -55oC
TJ = 175oC
75
TJ = 25oC
50
25
VGS = 4.5V
50
VGS = 4V
25
VGS = 3V
0
0
1
2
3
4
5
0
6
0.5
VGS , GATE TO SOURCE VOLTAGE (V)
1.5
2.0
Figure 6. Saturation Characteristics
2.0
25
ID = 32A
ID = 14A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = 50A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
1.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
20
15
10
1.5
1.0
VGS = 10V, ID = 50A
0.5
5
2
4
6
8
-80
10
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 7. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
1.2
1.2
VGS = VDS, ID = 250µA
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = 10V
75
ID, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
1.0
0.8
0.6
0.4
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE
160
200
(oC)
Figure 9. Normalized Gate Threshold Voltage vs
Junction Temperature
©2002 Fairchild Semiconductor Corporation
1.1
1.0
0.9
-80
-40
0
40
80
120
TJ , JUNCTION TEMPERATURE
160
200
(oC)
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
ISL9N312AD3 / ISL9N312AD3ST Rev C
ISL9N312AD3 / ISL9N312AD3ST
Typical Characteristic (Continued) TC = 25°C unless otherwise noted
10
2000
VDD = 15V
VGS , GATE TO SOURCE VOLTAGE (V)
CISS = CGS + CGD
C, CAPACITANCE (pF)
1000
COSS ≅ CDS + CGD
CRSS = CGD
VGS = 0V, f = 1MHz
100
0.1
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 32A
ID = 14A
2
0
1
30
10
0
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 11. Capacitance vs Drain to Source
Voltage
30
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
200
200
VGS = 10V, VDD = 15V, ID = 11A
VGS = 4.5V, VDD = 15V, ID = 11A
150
150
SWITCHING TIME (ns)
SWITCHING TIME (ns)
20
Qg, GATE CHARGE (nC)
tr
100
tf
td(OFF)
50
td(OFF)
100
tf
50
tr
td(ON)
0
td(ON)
0
0
10
20
30
40
50
0
RGS, GATE TO SOURCE RESISTANCE (Ω)
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Test Circuits and Waveforms
VDS
BVDSS
tP
VDS
L
IAS
VDD
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
©2002 Fairchild Semiconductor Corporation
Figure 16. Unclamped Energy Waveforms
ISL9N312AD3 / ISL9N312AD3ST Rev C
ISL9N312AD3 / ISL9N312AD3ST
Typical Characteristic (Continued) TC = 25°C unless otherwise noted
VDS
VDD
Qg(TOT)
RL
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
-
VGS = 1V
DUT
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
VDD
-
10%
10%
0
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 19. Switching Time Test Circuit
©2002 Fairchild Semiconductor Corporation
10%
Figure 20. Switching Time Waveforms
ISL9N312AD3 / ISL9N312AD3ST Rev C
ISL9N312AD3 / ISL9N312AD3ST
Test Circuits and Waveforms (Continued)
( T JM – T A )
P DM = ----------------------------Z θJA
125
RθJA = 33.32 + 23.84/(0.268+Area)
100
RθJA (oC/W)
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
75
(EQ. 1)
50
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
25
0.01
0.1
1
10
AREA, TOP COPPER AREA (in2)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
23.84
( 0.268 + Area )
R θ JA = 33.32 + -------------------------------------
©2002 Fairchild Semiconductor Corporation
(EQ. 2)
ISL9N312AD3 / ISL9N312AD3ST Rev C
ISL9N312AD3 / ISL9N312AD3ST
Thermal Resistance vs. Mounting Pad Area
.SUBCKT ISL9N312AD3ST 2 1 3 ;
rev May 2001
CA 12 8 9e-10
CB 15 14 9e-10
CIN 6 8 1.35e-9
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
10
5
51
EVTHRES
+ 19 8
+
LGATE
EVTEMP
RGATE +
18 22
9
20
GATE
1
ESLC
+
21
17
EBREAK 18
-
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2e-3
RGATE 9 20 1.76
RLDRAIN 2 5 10
RLGATE 1 9 56.1
RLSOURCE 3 7 19.8
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.8e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
11
50
RDRAIN
6
8
ESG
DBREAK
+
RSLC2
IT 8 17 1
S1A
S1B
S2A
S2B
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 31.6
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
LDRAIN 2 5 1e-9
LGATE 1 9 5.61e-9
LSOURCE 3 7 1.98e-9
DRAIN
2
5
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
12
13
S2A
S1B
CA
RBREAK
15
14
13
8
17
18
RVTEMP
S2B
13
CB
6
8
EGS
-
19
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*160),5))}
.MODEL DBODYMOD D (IS = 1.1e-11 N = 1.075 RS = 7.2e-3 TRS1 = 5e-4 TRS2 = 1e-6 CJO = 6.9e-10 TT = 8e-11 M = 0.49)
.MODEL DBREAKMOD D (RS = 0.95 TRS1 = 1e-3 TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 5e-10 IS = 1e-30 N = 10 M = 0.46)
.MODEL MMEDMOD NMOS (VTO = 1.99 KP = 6 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.76)
.MODEL MSTROMOD NMOS (VTO = 2.35 KP = 55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.62 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 17.6 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.1e-3 TC2 = -2e-6)
.MODEL RDRAINMOD RES (TC1 = 1.6e-2 TC2 = 1e-5)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 2.5e-5)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.1e-3 TC2 = -1e-5)
.MODEL RVTEMPMOD RES (TC1 = -1.8e-3 TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -3 VOFF= -1)
VON = -1 VOFF= -3)
VON = -0.3 VOFF= 0.2)
VON = 0.2 VOFF= -0.3)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
ISL9N312AD3 / ISL9N312AD3ST Rev C
ISL9N312AD3 / ISL9N312AD3ST
PSPICE Electrical Model
REV May 2001
template ISL9N312AD3ST n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 1.1e-11, nl = 1.075, rs = 7.2e-3, trs1 = 5e-4, trs2 = 1e-6, cjo = 6.9e-10, m=0.49, tt = 8e-11)
dp..model dbreakmod = (rs = 0.95, trs1 = 1e-3, trs2 = -8.9e-6)
dp..model dplcapmod = (cjo = 5e-10, isl=10e-30, nl=10, m=0.46)
m..model mmedmod = (type=_n, vto = 1.99, kp=6, is=1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.35, kp = 55, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.62, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -3, voff = -1)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1, voff = -3)
LDRAIN
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.2)
DRAIN
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.3) DPLCAP 5
RLDRAIN
RSLC1
51
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
LGATE
11
DBODY
EVTHRES
16
21
+ 19 8
+
GATE
1
DBREAK
50
-
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.61e-9
l.lsource n3 n7 = 1.98e-9
2
10
c.ca n12 n8 = 9e-10
c.cb n15 n14 = 9e-10
c.cin n6 n8 = 1.35e-9
EVTEMP
RGATE + 18 22
9
20
6
MWEAK
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
CIN
8
LSOURCE
SOURCE
3
7
RSOURCE
RLSOURCE
res.rbreak n17 n18 = 1, tc1 = 1.1e-3, tc2 = -2e-6
res.rdrain n50 n16 = 2e-3, tc1 = 1.6e-2, tc2 = 1e-5
res.rgate n9 n20 = 1.76
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 56.1
res.rlsource n3 n7 = 19.8
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 = 2.5e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.8e-3, tc1 = 1e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.8e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -2.1e-3, tc2 = -1e-5
S1A
12
13
S2A
S1B
CA
15
14
13
8
RBREAK
17
18
RVTEMP
S2B
13
CB
6
8
EGS
-
19
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 31.6
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/160))** 5))
}
}
©2002 Fairchild Semiconductor Corporation
ISL9N312AD3 / ISL9N312AD3ST Rev C
ISL9N312AD3 / ISL9N312AD3ST
SABER Electrical Model
th
JUNCTION
REV 23 May 2001
ISL9N312T
CTHERM1 th 6 1e-3
CTHERM2 6 5 1.5e-3
CTHERM3 5 4 1.9e-3
CTHERM4 4 3 3e-3
CTHERM5 3 2 8.5e-3
CTHERM6 2 tl 3.5e-2
RTHERM1 th 2.2e-3
RTHERM2 6 3e-3
RTHERM3 5 4 5e-2
RTHERM4 4 3 4.8e-1
RTHERM5 3 2 5e-1
RTHERM6 2 tl 6e-1
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model ISL9N312T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 1e-3
ctherm.ctherm2 6 5 = 1.5e-3
ctherm.ctherm3 5 4 = 1.9e-3
ctherm.ctherm4 4 3 = 3e-3
ctherm.ctherm5 3 2 = 8.5e-3
ctherm.ctherm6 2 tl = 3.5e-2
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
rtherm.rtherm1 th 6 = 2.2e-3
rtherm.rtherm2 6 5 = 3e-3
rtherm.rtherm3 5 4 = 5e-2
rtherm.rtherm4 4 3 = 4.8e-1
rtherm.rtherm5 3 2 = 5e-1
rtherm.rtherm6 2 tl = 6e-1
}
RTHERM5
CTHERM5
2
CTHERM6
RTHERM6
tl
©2002 Fairchild Semiconductor Corporation
CASE
ISL9N312AD3 / ISL9N312AD3ST Rev C
ISL9N312AD3 / ISL9N312AD3ST
SPICE Thermal Model
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