KM4211IM8TR3

www.fairchildsemi.com KM4211 Dual, 0.2mA, Low Cost, +2.7V & +5V, 35MHz Rail-to-Rail Amp Features I I I I I I I I I I I General Description The KM4211 is a dual ultra-low power, low cost, voltage feedback amplifier. The KM4211 uses only 208µA of supply current per amplifier and is designed to operate from 2.5V to 5.5V or ±1.25V to ±2.75V supplies. The input voltage range extends 300mV below the negative rail and 1.2V below the positive rail. The KM4211 offers high bipolar performance at a low CMOS price. The KM4211 offers superior dynamic performance with a 35MHz small signal bandwidth and 27V/µs slew rate. The combination of low power, high bandwidth, and rail-to-rail performance make the KM4211 well suited for battery-powered communication/computing systems. The KM4112 (single) and KM4121 (single with disable) are also available. Non-Inverting Freq. Response Vs = +5V Normalized Magnitude (2dB/div) 0.1 G=2 208µA supply current 35MHz bandwidth Fully specified at +2.7V and +5V supplies Output voltage range: 0.08V to 4.88V; Vs = +5 Input voltage range: -0.3V to +3.8V; Vs = +5 27V/µs slew rate ±8.5mA linear output current ±13mA short circuit output current 21nV/√Hz input voltage noise Directly replaces OPA2350, MAX4132, MAX4281 Small package options (SOIC-8 and MSOP-8) Applications I I I I I I I I I I I A/D buffer Smart card readers Active filters Keyless entry Signal conditioning ASCI input devices Portable test instruments PCMUA cards Portable communications Bar-code readers Portable/battery-powered applications KM4211 Packages SOIC-8 Out1 -In1 +In1 -Vs 1 2 3 4 + 8 7 + +Vs Out2 -In2 +In2 1 10 100 Frequency (MHz) 6 5 MSOP-8 Out1 -In1 +In1 -Vs 1 2 3 4 + 8 7 + +Vs Out2 -In2 +In2 6 5 REV. 1 June 2001 DATA SHEET KM4211 KM4211 Electrical Characteristics (Vs = +2.7V, G = 2, RL = 2kΩ to Vs/2, Rf = 2.5kΩ; unless noted) PARAMETERS Case Temperature Frequency Domain Response -3dB bandwidth full power bandwidth gain bandwidth product Time Domain Response rise and fall time settling time to 0.1% overshoot slew rate Distortion and Noise Response 2nd harmonic distortion 3rd harmonic distortion THD input voltage noise crosstalk DC Performance input offset voltage average drift input bias current average drift input offset current power supply rejection ratio open loop gain quiescent current Input Characteristics input resistance input capacitance input common mode voltage range common mode rejection ratio Output Characteristics output voltage swing linear output current short circuit output current power supply operating range G = +1, Vo = 0.05Vpp G = +2, Vo < 0.2Vpp G = -1, Vo = 2Vpp 0.2V step 1V step 2V step, G = -1 2V step, G = -1 1Vpp, 100kHz 1Vpp, 100kHz 1Vpp, 100kHz >10kHz 100kHz, Vo = 0.2Vpp CONDITIONS TYP +25°C 28 15 7 16 20 140 10 1.5 -0.3 to 1.5 92 0.06 to 2.62 0.08 to 2.6 ±8 ±12.5 2.7 ±5 1.3 130 56 56 245 MIN & MAX +25°C MHz MHz MHz MHz ns ns % V/µs dBc dBc dB nV/√Hz dB mV µV/°C µA nA/°C nA dB dB µA MΩ pF V dB V V mA mA V 2 2 2 2 2 2 1 UNITS NOTES DC DC, Vcm = 0V to Vs - 1.5 RL = 10kΩ to Vs/2 RL = 2kΩ to Vs/2 65 2 0.2 to 2.4 2.5 to 5.5 2 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. NOTES: 1) For G = +1, Rf = 0. 2) 100% tested at +25°C. Absolute Maximum Ratings supply voltage 0 to +6V maximum junction temperature +175°C storage temperature range -65°C to +150°C lead temperature (10 sec) +260°C operating temperature range (recommended) -40°C to +85°C input voltage range +Vs +0.5V; -Vs -0.5V internal power dissipation see power derating curves Package Thermal Resistance Package 8 lead SOIC 8 lead MSOP θJA 152°C/W 206°C/W 2 REV. 1 June 2001 KM4211 DATA SHEET KM4211 Electrical Characteristics (Vs = +2.7V, G = 2, RL = 2kΩ to Vs/2, Rf = 2.5kΩ; unless noted) PARAMETERS Case Temperature Frequency Domain Response -3dB bandwidth full power bandwidth gain bandwidth product Time Domain Response rise and fall time settling time to 0.1% overshoot slew rate Distortion and Noise Response 2nd harmonic distortion 3rd harmonic distortion THD input voltage noise crosstalk DC Performance input offset voltage average drift input bias current average drift input offset current power supply rejection ratio open loop gain quiescent current Input Characteristics input resistance input capacitance input common mode voltage range common mode rejection ratio Output Characteristics output voltage swing linear output current short circuit output current power supply operating range G = +1, Vo = 0.05Vpp G = +2, Vo < 0.2Vpp G = -1, Vo = 2Vpp 0.2V step 2V step 2V step, G = -1 2V step, G = -1 2Vpp, 100kHz 2Vpp, 100kHz 2Vpp, 100kHz >10kHz 100kHz, Vo = 0.2Vpp CONDITIONS TYP +25°C 35 18 8 20 18 140 10 1.35 -0.3 to 3.8 85 0.08 to 4.88 0.1 to 4.8 ±8.5 ±13 5 MIN & MAX +25°C MHz MHz MHz MHz ns ns % V/µs dBc dBc dB nV/√Hz dB mV µV/°C µA nA/°C nA dB dB µA MΩ pF V dB V V mA mA V 1 UNITS NOTES DC DC, Vcm = 0V to Vs - 1.5 RL = 10kΩ to Vs/2 RL = 2kΩ to Vs/2 2.5 to 5.5 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. NOTES: 1) For G = +1, Rf = 0. REV. 1 June 2001 3 DATA SHEET KM4211 KM4211 Performance Characteristics (Vs = +5V, G = 2, RL = 2kΩ to Vs/2, Rf = 2.5kΩ; unless noted) Non-Inverting Frequency Response Vs = +5V Normalized Magnitude (2dB/div) Normalized Magnitude (1dB/div) G=2 G=1 Rf = 0 Inverting Frequency Response Vs = +5V G = -1 G = -2 G = 10 G = -10 G = -5 G=5 0.1 1 10 100 0.1 1 10 100 Frequency (MHz) Non-Inverting Freq. Response Vs = +2.7V Normalized Magnitude (2dB/div) G=2 G=1 Rf = 0 Frequency (MHz) Inverting Frequency Response Vs = +2.7V Normalized Magnitude (1dB/div) G = -1 G = -2 G = -10 G = 10 G = -5 G=5 0.1 1 10 100 0.1 1 10 100 Frequency (MHz) Large Signal Frequency Response 100 |Gain| Frequency (MHz) Open Loop Gain & Phase vs. Frequency 40 Open Loop Phase (deg) Vo = 1Vpp Open Loop Gain (dB) Magnitude (1dB/div) 80 60 40 20 0 Phase 0 -40 -80 -120 -160 -200 10 100 1k 10k 100k 1M 10M Vo = 2Vpp -20 0.1 1 10 100 Frequency (MHz) Input Voltage Noise 100 -40 Vo = 2Vpp Frequency (Hz) 2nd & 3rd Harmonic Distortion; Vs = +5V Voltage Noise (nV/√Hz) 80 -50 Distortion (dBc) 3rd -60 -70 -80 -90 2nd 60 40 20 0 100 1k 10k 100k 1M -100 10 100 1000 Frequency (Hz) Frequency (kHz) 4 REV. 1 June 2001 KM4211 KM4211 DATA SHEET KM4211 Performance Characteristics (Vs = +5V, G = 2, RL = 2kΩ to Vs/2, Rf = 2.5kΩ; unless noted) 2nd & 3rd Harmonic Distortion; Vs = +2.7V -40 Vo = 1Vpp PSRR 10 0 -50 Distortion (dBc) 3rd -10 PSRR (dB) 2nd -60 -70 -80 -90 -20 -30 -40 -50 -60 -70 -100 10 100 1000 100 1k 10k 100k 1M 10M Frequency (kHz) CMRR -20 -30 -40 4.85 4.80 Frequency (Hz) Output Swing vs. RL -50 -60 -70 -80 -90 -100 10 100 1k 10k 100k 1M 10M Output Swing (Vpp) CMRR (dB) 4.75 4.70 4.65 4.60 4.55 1 10 100 Frequency (Hz) Small Signal Pulse Response Vs = +5V Output Voltage (0.05V/div) Output Voltage (0.5V/div) RL (kΩ) Large Signal Pulse Response Vs = +5V Time (1µs/div) Time (1µs/div) Crosstalk vs. Frequency -65 -70 -75 Crosstalk (dB) -80 -85 -90 -95 -100 -105 0.01 0.1 1 10 Frequency (MHz) REV. 1 June 2001 5 DATA SHEET KM4211 General Description The KM4211 is a single supply, general purpose, voltagefeedback amplifier fabricated on a complementary bipolar process. The KM4211 offers 35MHz unity gain bandwidth, 27V/µs slew rate, and only 208µA supply current. It features a rail-to-rail output stage and is unity gain stable. The design utilizes a patent pending topology that provides increased slew rate performance. The common mode input range extends to 300mV below ground and to 1.2V below Vs. Exceeding these values will not cause phase reversal. However, if the input voltage exceeds the rails by more than 0.5V, the input ESD devices will begin to conduct. The output will stay at the rail during this overdrive condition. The design uses a Darlington output stage. The output stage is short circuit protected and offers “soft” saturation protection that improves recovery time. The typical circuit schematic is shown in Figure 1. The KM4211 is short circuit protected. However, this may not guarantee that the maximum junction temperature (+150°C) is not exceeded under all conditions. Follow the maximum power derating curves shown in Figure 2 to ensure proper operation. Maximum Power Dissipation Maximum Power Dissipation (W) 2.0 1.5 SOIC-8 lead 1.0 MSOP-8 lead 0.5 0 -50 -30 -10 10 30 50 70 90 Ambient Temperature ( C) Figure 2: Power Derating Curves Overdrive Recovery For an amplifier, an overdrive condition occurs when the output and/or input ranges are exceeded. The recovery time varies based on whether the input or output is overdriven and by how much the ranges are exceeded. The KM4211 will typically recover in less than 20ns from an overdrive condition. Figure 3 shows the KM4111 in an overdriven condition. +Vs 6.8µF + In + Rg 0.01µF Out Rf KM4211 Output Voltage (0.5V/div) Input Voltage (0.2V/div) Input Output Figure 1: Typical Configuration Enable/Disable Function (KM4121) The KM4121 offers an active-low disable pin that can be used to lower its supply current. Leave the pin floating to enable the part. Pull the disable pin to the negative supply (which is ground in a single supply application) to disable the output. During the disable condition, the nominal supply current will drop to below 40µA and the output will be at high impedance with about 2pF capacitance. Power Dissipation The maximum internal power dissipation allowed is directly related to the maximum junction temperature. If the maximum junction temperature exceeds 150°C, some reliability degradation will occur. If the maximum junction temperature exceeds 175°C for an extended time, device failure may occur. 6 Time (1µs/div) Figure 3: Overdrive Recovery Driving Capacitive Loads A small series resistance (Rs) at the output of the amplifier, illustrated in Figure 4, will improve stability and settling performance. REV. 1 June 2001 KM4211 DATA SHEET + Rf Rg Rs CL RL Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of this device: Eval Board KEB006 KEB010 Description Dual Channel, Dual Supply 8 lead SOIC Dual Channel, Dual Supply 8 lead MSOP Products KM4211IC8 KM4211IM8 Figure 4: Typical Topology for driving a capacitive load Layout Considerations General layout and supply bypassing play major roles in high frequency performance. Fairchild has evaluation boards to use as a guide for high frequency layout and to aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: Include 6.8µF and 0.01µF ceramic capacitors Place the 6.8µF capacitor within 0.75 inches of the power pin I Place the 0.01µF capacitor within 0.1 inches of the power pin I Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance I Minimize all trace lengths to reduce series inductances I I Evaluation board schematics and layouts are shown in Figure 5 and Figure 6. The KEB006 evaluation board is built for dual supply operation. Follow these steps to use the board in a single supply application: 1. Short -Vs to ground 2. Use C3 and C4, if the -Vs pin of the KM4111 or KM4121 is not directly connected to the ground plane. Refer to the evaluation board layouts shown in Figure 6 for more information. When evaluating only one channel, complete the following on the unused channel 1. Ground the non-inverting input 2. Short the output to the inverting input Figure 5: Evaluation Board Schematic REV. 1 June 2001 7 DATA DATA SHEET KM4211 KM4211 Evaluation Board Layout Figure 6a: KEB006 (top side) Figure 6b: KEB006 (bottom side) Figure 6c: KEB010 (top side) Figure 6d: KEB010 (bottom side) 8 REV. 1 June 2001 KM4211 KM4211 DATA SHEET KM4211 Package Dimensions SOIC-8 D e ZD C L 7¡ SYMBOL A1 B C D E e H h L A ZD A2 L MIN MAX 0.10 0.25 0.36 0.46 0.19 0.25 4.80 4.98 3.81 3.99 1.27 BSC 5.80 6.20 0.25 0.50 0.41 1.27 1.52 1.72 8 0 0.53 ref 1.37 1.57 SOIC C L E H Pin No. 1 B DETAIL-A h x 45¡ NOTE: DETAIL-A 1. All dimensions are in millimeters. 2. Lead coplanarity should be 0 to 0.10mm (.004") max. 3. Package surface finishing: (2.1) Top: matte (charmilles #18~30). (2.2) All sides: matte (charmilles #18~30). (2.3) Bottom: smooth or matte (charmilles #18~30). 4. All dimensions excluding mold flashes and end flash from the package body shall not exceed o.152mm (.006) per side(d). A A1 A2 α C e S 02 MSOP-8 t1 SYMBOL MIN A 1.10 A1 0.10 A2 0.86 D 3.00 D2 2.95 E 4.90 E1 3.00 E2 2.95 E3 0.51 E4 0.51 R 0.15 R1 0.15 t1 0.31 t2 0.41 b 0.33 b1 0.30 c 0.18 c1 0.15 01 3.0° 02 12.0° 03 12.0° L 0.55 L1 0.95 BSC aaa 0.10 bbb 0.08 ccc 0.25 e 0.65 BSC S 0.525 BSC MAX – ±0.05 ±0.08 ±0.10 ±0.10 ±0.15 ±0.10 ±0.10 ±0.13 ±0.13 +0.15/-0.06 +0.15/-0.06 ±0.08 ±0.08 +0.07/-0.08 ±0.05 ±0.05 +0.03/-0.02 ±3.0° ±3.0° ±3.0° ±0.15 – – – – – – MSOP E/2 2X –H– R1 t2 R Gauge Plane E1 3 7 0.25mm –B– 2 03 b L1 c1 b1 Section A - A 5 L 01 E3 E4 1 2 2 4 6 ccc A B C c D2 A2 –C– Detail A Scale 40:1 Detail A E2 A b aaa A bbb M A B C –A– A A E1 E A1 D 3 4 NOTE: 1 All dimensions are in millimeters (angle in degrees), unless otherwise specified. 2 3 4 5 6 7 Datums – B – and – C – to be determined at datum plane – H – . Dimensions "D" and "E1" are to be determined at datum – H – . Dimensions "D2" and "E2" are for top package and dimensions "D" and "E1" are for bottom package. Cross sections A – A to be determined at 0.13 to 0.25mm from the leadtip. Dimension "D" and "D2" does not include mold flash, protrusion or gate burrs. Dimension "E1" and "E2" does not include interlead flash or protrusion. REV. 1 June 2001 9 DATA SHEET KM4211 Ordering Information Model KM4211 KM4211 KM4211 KM4211 Part Number KM4211IC8 KM4211IC8TR3 KM4211IM8 KM4211IM8TR3 Package SOIC-8 SOIC-8 MSOP-8 MSOP-8 Container Rail Reel Rail Reel Pack Qty 95 2500 50 4000 Temperature range for all parts: -40°C to +85°C DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com © 2001 Fairchild Semiconductor Corporation