MBR05S0L

FAN5234 — Dual Mobile-Friendly PWM / PFM Controller November 2010 FAN5234 Dual Mobile-Friendly PWM / PFM Controller Features W ide Input Voltage Range for Mobile Systems: 2V to 24V Excellent Dynamic Response with Voltage FeedForward and Average-Current-Mode Control Lossless Current Sensing on Low-Side MOSFET or Precision Over-Current via Sense Resistor VCC Under-Voltage Lockout Power-Good Signal Light-Load Hysteretic Mode Maximizes Efficiency 300KHz or 600KHz Operation TSSOP16 Package Description The FAN5234 PWM controller provides high efficiency and regulation with an adjustable output from 0.9V to 5.5V required to power I/O, chip-sets, memory banks, or peripherals in high-performance notebook computers, PDAs, and internet appliances. Synchronous rectification and hysteretic operation at light loads contribute to a high efficiency over a wide range of loads. The Hysteretic Mode of operation can be disabled if PWM Mode is desired for all load levels. Efficiency is further enhanced by using the MOSFET’s RDS(ON) as a current-sense component. Feed-forward ramp modulation, average current mode control, and internal feedback compensation provide fast response to load transients. The FAN5234 monitors these outputs and generates a PGOOD (power-good) signal when the soft-start is completed and the output is within ±10% of its set point. A built-in over-voltage protection prevents the output voltage from going above 120% of the set point. Normal operation is automatically restored when the over-voltage conditions cease. Under-voltage protection latches the chip off when the output drops below 75% of its set value after the softstart sequence is completed. An adjustable over-current function monitors the output current by sensing the voltage drop across the lower MOSFET. Applications Mobile PC Regulator Handheld PC Power Related Resources Application Note — AN-6002 Component Calculations and Simulation Tools for FAN5234 or FAN5236 Application Note — AN-1029 Maximum Power Enhancement Techniques for SO-8 Power MOSFET Ordering Information Part Number FAN5234MTCX Operating Temperature Range -10 to +85°C Package 16-Lead, Thin-Shrink Small-Outline Package (TSSOP) Packing Method Tape and Reel © 2004 Fairchild Semiconductor Corporation FAN5234 • Rev. 2.0.0 www.fairchildsemi.com FAN5234 — Dual Mobile-Friendly PWM / PFM Controller Typical Application VIN (BAT TERY) = 2 to 24V 1 VIN BO OT C1 D1 C5 L1 Q1B 10 9 12 6 LDRV PGND ISNS VSEN VOUT 15 C2 +5 +5 C4 R5 VCC 11 FA N5 234 14 ILIM EN 4 3 7 16 8 2 5 13 SW Q1A HDRV 1.8V at 3.5A R1 C6 +5 C3 R4 SS1 FPWM AGND PGOOD R3 R2 Figure 1. 1.18V Output Regulator Block Diagram Figure 2. Block Diagram © 2004 Fairchild Semiconductor Corporation FAN5234 • Rev. 2.0.0 www.fairchildsemi.com 2 FAN5234 — Dual Mobile-Friendly PWM / PFM Controller Pin Configuration VIN PGOOD EN ILIM VOUT VSEN SS AGND 1 2 3 4 5 6 7 8 FA N5234 16 15 14 13 12 11 10 9 FPWM BOOT HDRV SW ISNS VCC LDRV PGND Figure 3. Pin Configuration Pin Definitions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VIN PGOOD EN ILIM VOUT VSEN SS AGND PGND LDRV VCC ISNS SW HDRV BOOT FPWM Description Input Voltage. Connect to main input power source (battery), also used to program operating frequency for low input voltage operation (see Table 1). Power-Good Flag. An open-drain output that pulls LOW when VSEN is outside of a ±10% range of the 0.9V reference. Enable. Enables operation when pulled to logic HIGH. Toggling EN resets the regulator after a latched fault condition. This is a CMOS input whose state is indeterminate if left open. Current Limit. A resistor from this pin to GND sets the current limit. Output Voltage. Connect to output voltage. Used for regulation to ensure a smooth transition during mode changes. When VOUT is expected to exceed VCC, tie this pin to VCC. Output Voltage Sense. The feedback from the output. Used for regulation as well as power-good, under-voltage, and over-voltage protection monitoring. Soft-Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization, when this pin is charged with a 5µA current source. Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. Power Ground. The return for the low-side MOSFET driver output. Connect to the gate of the low-side MOSFET. Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to the gate of the low-side MOSFET. Supply Voltage. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling). Current-Sense Input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback. Switching Node. Return for the high-side MOSFET driver and a current-sense input. Connect to source of high-side MOSFET and low-side MOSFET drain. High-Side Drive. High-side (upper) MOSFET driver output. Connect to the gate of the highside MOSFET. BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 2. Forced PWM Mode. When logic HIGH, inhibits the regulation from entering Hysteretic Mode. © 2004 Fairchild Semiconductor Corporation FAN5234 • Rev. 2.0.0 www.fairchildsemi.com 3 FAN5234 — Dual Mobile-Friendly PWM / PFM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN Parameter VCC Supply Voltage VIN Supply Voltage BOOT, SW, ISNS, HDRV Pins BOOT to SW Pins All Other Pins Min. Max. 6.5 27 33 6.5 Unit V V V V V ºC ºC ºC -0.3 -10 -65 VCC+0.3 +150 +150 +300 TJ TSTG TL Junction Temperature Storage Temperature Lead Soldering Temperature, 10 Seconds Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC VIN TA ΘJA Parameter VCC Supply Voltage VIN Supply Voltage Ambient Temperature Thermal Resistance, Junction to Ambient Min. 4.75 -10 Typ. 5.00 Max. 5.25 24 +85 112 Unit V V °C °C/W © 2004 Fairchild Semiconductor Corporation FAN5234 • Rev. 2.0.0 www.fairchildsemi.com 4 FAN5234 — Dual Mobile-Friendly PWM / PFM Controller Electrical Characteristics Recommended operating conditions, unless otherwise noted. Symbol Power Supplies Parameter Conditions LDRV, HDRV Open; VSEN Forced Above Regulation Point Shutdown (EN-0) VIN Pin = Input Voltage Source VIN Pin = GND Rising VCC Falling Min. Typ. Max. Units IVCC VCC Current 850 5 10 7 4.30 4.10 0.1 20 15 4.55 4.27 1300 15 30 20 1 4.75 4.50 0.5 µA µA µA µA µA V V ISINK ISOURCE ISD VUVLO VUVLOH Oscillator fosc VPP VRAMP G VIN Current, Sinking VIN Current, Sourcing VIN Current, Shutdown UVLO Threshold UVLO Hysteresis Frequency Ramp Amplitude Ramp Offset Ramp / VIN Gain VIN > 5V VIN = 0V VIN = 16V VIN > 5V VIN ≥ 3V 1V < VIN < 3V 255 510 300 600 2 1.25 0.5 125 250 345 690 KHz V V mV/V Reference and Soft-Start VREF ISS VSS Internal Reference Voltage Soft-Start Current Soft-Start Complete Threshold IOUT from 0 to 3A, VIN from 2 to 24V At Startup 0.891 0.900 5 1.5 0.909 V µA V PWM Converter Load Regulation ISEN VSEN Bias Current VOUT Pin Input Impedance UVLOTSD Under-Voltage Shutdown ISNS UVLO Over-Current Threshold Over-Voltage Threshold % of Set Point, 2µs Noise Filter RILIM = 68.5KΩ, Figure 6 % of Set Point, 2µs Noise Filter Sourcing Sinking Sourcing Sinking -1 50 40 70 115 113 80 55 75 144 +1 150 65 80 172 120 % nA KΩ % % µA Output Drivers HDRV Output Resistance LDRV Output Resistance 8.0 3.2 8.0 1.5 15.0 4.0 15.0 2.4 Ω Ω Continued on following page… © 2004 Fairchild Semiconductor Corporation FAN5234 • Rev. 2.0.0 www.fairchildsemi.com 5 FAN5234 — Dual Mobile-Friendly PWM / PFM Controller Electrical Characteristics (Continued) Symbol Parameter Conditions % of Set Point, 2µs Noise Filter % of Set Point, 2µs Noise Filter IPGOOD = 4mA VPULLUP = 5V 1.5 Min. Typ. Max. Units Power-Good Output and Control Pins Lower Threshold Upper Threshold PGOOD Output Low Leakage Current Soft-Start Voltage, PGOOD Enabled EN, FPWM Inputs VINH VINL Input High Input Low 2 0.8 V V 86 110 92 115 0.5 1 % % V µA % VREF2 © 2004 Fairchild Semiconductor Corporation FAN5234 • Rev. 2.0.0 www.fairchildsemi.com 6 FAN5234 — Dual Mobile-Friendly PWM / PFM Controller Functional Description Overview The FAN5234 is a PWM controller intended for lowvoltage power applications in notebook, desktop, and sub-notebook PCs. The output voltage of the controller can be set in the range of 0.9V to 5.5V by an external resistor divider. The synchronous buck converter can operate from an unregulated DC source (such as a notebook battery), with voltage ranging from 2V to 24V, or from a regulated system rail. In either case, the IC is biased from a +5V source. The PWM modulator uses an average-currentmode control with input voltage feed-forward for simplified feedback loop compensation and improved line regulation. The controller includes integrated feedback loop compensation that dramatically reduces the number of external components. Depending on the load level, the converter can operate in fixed-frequency PWM Mode or in Hysteretic Mode. Switch-over from PWM to Hysteretic Mode improves the converters' efficiency at light loads and prolongs battery run time. In Hysteretic Mode, a comparator is synchronized to the main clock to allow seamless transition between the operational modes and reduced channel-to-channel interaction. The Hysteretic Mode of operation can be inhibited independently using the FPWM pin if variable frequency operation is not desired. When SS reaches 1.5V, the power-good outputs are enabled and Hysteretic Mode is allowed. The converter is forced into PWM Mode during soft-start. Operation Mode Control The mode-control circuit changes the converter’s mode from PWM to Hysteretic and vice versa based on the voltage polarity of the SW node when the lower MOSFET is conducting and just before the upper MOSFET turns on. For continuous inductor current, the SW node is negative when the lower MOSFET is conducting and the converters operate in fixedfrequency PWM Mode, as shown in Figure 4. This mode achieves high efficiency at nominal load. When the load current decreases to the point where the inductor current flows through the lower MOSFET in the “reverse” direction, the SW node becomes positive and the mode is changed to Hysteretic, which achieves higher efficiency at low currents by decreasing the effective switching frequency. To prevent accidental mode change or "mode chatter," the transition from PWM to Hysteretic Mode occurs when the SW node is positive for eight consecutive clock cycles (see Figure 4). The polarity of the SW node is sampled at the end of the lower MOSFET conduction time. At the transition between PWM and Hysteretic Mode, both the upper and lower MOSFETs are turned off. The SW node “rings” based on the output inductor and the parasitic capacitance on the SW node and settles out at the value of the output voltage. The boundary value of inductor current, where current becomes discontinuous, is estimated by the following: Oscillator Table 1. Converter Operating Modes Mode Battery Fixed 300 Fixed 600 fSW Converter Power 300 300 600 2 to 24V 1.2 x 1.25 x 1.6 x 3.5A operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1V. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1V. This allows a wide variety of upper and lower MOSFETs to be used without concern for simultaneous conduction or shoot-through. There must be a low-resistance, low-inductance path between the driver pin and the MOSFET gate for the adaptive dead-time circuit to work properly. Any delay along that path subtracts from the delay generated by the adaptive dead-time circuit and shoot-through may occur. ≈ 8.5A (6) Duty Cycle Clamp During severe load increase, the error amplifier output can go to its upper limit, pushing a duty cycle to almost 100% for a significant amount of time. This could cause a large increase of the inductor current and lead to a long recovery from a transient over-current condition or even to a failure at high input voltages. To prevent this, the output of the error amplifier is clamped to a fixed value after two clock cycles if severe output voltage excursion is detected, limiting maximum duty cycle to: DC MAX = V OUT V IN ⎛ 2 .4 +⎜ ⎜V ⎝ IN ⎞ ⎟ ⎟ ⎠ Frequency Loop Compensation Due to the implemented current-mode control, the modulator has a single-pole response with -1 slope at frequency determined by load. Therefore: f PO = 1 2 π ROCO (8) (7) where RO is load resistance and CO is load capacitance. For this type of modulator, type-2 compensation circuit is usually sufficient. To reduce the number of external components and simplify the design task, the PWM controller has an internally compensated error amplifier. Figure 7 shows a type two amplifier, its response, and the responses of a current mode modulator and the converter. The type-2 amplifier, in addition to the pole at the origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole. www.fairchildsemi.com 9 This is designed to not interfere with normal PWM operation. When FPWM is grounded, the duty cycle clamp is disabled and the maximum duty cycle is 87%. Gate Driver The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals, providing necessary amplification, level shifting, and shoot-through protection. It also has functions that help optimize the IC performance over a wide range of © 2004 Fairchild Semiconductor Corporation FAN5234 • Rev. 2.0.0 FAN5234 — Dual Mobile-Friendly PWM / PFM Controller C2 R2 C1 VIN R1 REF EA Out Err o ra mp . Over-Current Sensing If the circuit's current-limit signal (“ILIM det” in Figure 6) is HIGH at the beginning of a clock cycle, a pulseskipping circuit is activated and HDRV is inhibited. The circuit continues to pulse skip in this manner for the next eight clock cycles. If at any time from the ninth to the sixteenth clock cycle, the ILIM det is again reached, the over-current protection latch is set, disabling the chip. If ILIM det does not occur between cycles 9 and 16, normal operation is restored and the over-current circuit resets itself. C on ve rt e r Modulator 18 14 0 1 f P0 PGOOD IL 8 CLK f Z f P 2 Figure 7. Compensation fZ = 1 = 6kHz 2π R2C1 (9) 3 VOUT 1 fP = = 600kHz 2π R2C 2 (10) This region is also associated with phase “bump” or reduced phase shift. The amount of phase shift reduction depends the width of the region of flat gain and has a maximum value of 90°. To further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feed-forward of VIN to the oscillator ramp. The zero frequency, the amplifier high-frequency gain, and the modulator gain are chosen to satisfy most typical applications. The crossover frequency appears at the point where the modulator attenuation equals the amplifier high-frequency gain. The system designer must specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation, plenty of phase margin is achieved due to zero-pole pair phase “boost.” Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 10kHz to 50kHz range gives some additional phase boost. There is an opposite trend in mobile applications to keep the output capacitor as small as possible. CH1 5.0V CH3 2.0AW CH2 100mV M 10.0s Figure 8. Over-Current Protection Waveforms Over-Voltage / Under-Voltage Protection Should the VSEN voltage exceed 120% of VREF (0.9V) due to an upper MOSFET failure or for other reasons, the over-voltage protection comparator forces LDRV HIGH. This action actively pulls down the output voltage and, in the event of the upper MOSFET failure, eventually blows the battery fuse. As soon as the output voltage drops below the threshold, the OVP comparator is disengaged. This OVP scheme provides a ‘soft’ crowbar function to tackle severe load transients and does not invert the output voltage when activated — a common problem for latched OVP schemes. Similarly, if an output short-circuit or severe load transient causes the output to droop to less than 75% of its regulation set point, the regulator shuts down. Over-Temperature Protection The chip incorporates an over-temperature protection circuit that shuts the chip down when a die temperature reaches 150°C. Normal operation is restored at die temperature below 125°C with internal power on reset asserted, resulting in a full soft-start cycle. Protections The converter output is monitored and protected against extreme overload, short circuit, over-voltage, and under-voltage conditions. A sustained overload on an output sets the PGOOD pin LOW and latches off the chip. Operation is restored by cycling the VCC voltage or by toggling the EN pin. If VOUT drops below the under-voltage threshold, the chip shuts down immediately. © 2004 Fairchild Semiconductor Corporation FAN5234 • Rev. 2.0.0 www.fairchildsemi.com 10 FAN5234 — Dual Mobile-Friendly PWM / PFM Controller Design and Component Selection Guidelines As an initial step, define operating input voltage range, output voltage, and minimum and maximum load currents for the controller. For the examples in the following discussion, select components for: VIN from 5V to 20V VOUT = 1.8V at ILOAD(MAX) = 3.5A Output Capacitor Selection The output capacitor serves two major functions in a switching power supply. Along with the inductor, it filters the sequence of pulses produced by the switcher and it supplies the load transient currents. The output capacitor requirements are usually dictated by ESR, inductor ripple current (ΔI), and the allowable ripple voltage (ΔV): ESR < Setting the Output Voltage The internal reference is 0.9V. The output is divided down by a voltage divider to the VSEN pin (for example, R1 and R2 in Figure 1). The output voltage therefore is: 0.9 V V OUT − 0.9 V = R2 R1 ΔV ΔI ΔV 0.1V = = 142mΩ ΔI 0.7 A (17) For this example, ESR(MAX ) = (11) To minimize noise pickup on this node, keep the resistor to GND (R2) below 2K; for example R2 at 1.82K, then choose R5: R5 = In addition, the capacitor's ESR must be low enough to allow the converter to stay in regulation during a load step. The ripple voltage due to ESR for the converter in Figure 1 is 100mVPP. Some additional ripple will appear due to the capacitance value itself: ΔV = (1.82 KΩ ) × (1.8V − 0.9 ) = 1.82 K 0. 9 ΔI COUT × 8 × fSW (18) (12) which is only about 1.5mV for the converter in Figure 1 and can be ignored. The capacitor must also be rated to withstand the RMS current, which is approximately 0.3 X (ΔI) or about 210mA for the converter in Figure 1. High-frequency decoupling capacitors should be placed as close to the loads as physically possible. Output Inductor Selection The minimum practical output inductor value keeps inductor current just on the boundary of continuous conduction at some minimum load. The industry standard practice is to choose the ripple current to be somewhere from 15% to 35% of the nominal current. At light-load, the ripple current determines the point where the converter automatically switches to Hysteretic Mode to sustain high efficiency. The following equations help to choose the proper value of the output filter inductor: ΔI = 2 − 1MIN ΔV = OUT Input Capacitor Selection The input capacitor should be selected by its ripple current rating. The input RMS current at maximum load current (IL) is: ESR (13) IRMS = I L D − D 2 (19) where ΔI is the inductor ripple current, which is chosen for 20% of the full load current and ΔVOUT is the maximum output ripple voltage allowed: where the converter duty cycle; D = L= VIN − V OUT f SW × ΔI × V OUT VIN VOUT , which for VIN the circuit in Figure 1, with VIN=6, calculates to IRMS = 1.6A . (14) Power MOSFET Selection Losses in a MOSFET are the sum of its switching (PSW ) and conduction (PCOND) losses. For this example, use: VIN = 20V, VOUT = 1.8V ∆I = 20% x 3.5A = 0.7A fSW = 300KHz. Therefore; L ≈8µH (16) (15) In typical applications, the FAN5234 converter's output voltage is low with respect to its input voltage. Therefore, the lower MOSFET (Q2) is conducting the full-load current for most of the cycle. Q2 should therefore be selected to minimize conduction losses, thereby selecting a MOSFET with low RDS(ON). In contrast, the high-side MOSFET (Q1) has a shorter duty cycle, and its conduction loss has less impact. Q1, however, sees most of the switching losses, so Q1's primary selection criteria should be gate charge. © 2004 Fairchild Semiconductor Corporation FAN5234 • Rev. 2.0.0 www.fairchildsemi.com 11 FAN5234 — Dual Mobile-Friendly PWM / PFM Controller High-Side Losses Figure 9 shows a MOSFET's switching interval, with the upper graph being the voltage and current on the drainto-source and the lower graph detailing VGS vs. time with a constant current charging the gate. The x-axis therefore is also representative of gate charge (QG). CISS = CGD + CGS, and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). The gate charge (QG) parameters on the lower graph are either specified or can be derived from MOSFET datasheets. The driver’s impedance and CISS determine t2 while t3’s period is controlled by the driver's impedance and QGD. Since most of tS occurs when VGS = VSP, use a constant current assumption for the driver to simplify the calculation of tS: ts = Q G( SW ) I DRIVER = Q G( SW ) ⎛ V −V CC SP ⎜ ⎜R + R GATE ⎝ DRIVER ⎞ ⎟ ⎟ ⎠ (23) Assuming switching losses are about the same for both the rising edge and falling edge, Q1's switching losses, occur during the shaded time when the MOSFET has voltage across it and current through it. These losses are given by: PUPPER = PSW + PCOND where: (20) Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: QG(SW) = QGD + QGS – QTH (24) where QTH is the gate charge required to get the MOSFET to its threshold (VTH). For the high-side MOSFET, VDS = VIN, which can be as high as 20V in a typical portable application. Care should be taken to include the delivery of the MOSFET's gate power (PGATE) in calculating the power dissipation required for the FAN5234: PG ATE ⎞ ⎛ V ×I PSW = ⎜ DS L × 2 × t s ⎟ f SW ⎟ ⎜ 2 ⎠ ⎝ ⎛V PCOND = ⎜ OUT ⎜V ⎝ IN ⎞ ⎟×I 2 ×R DS ( ON ) ⎟ OUT ⎠ (21) (22) PUPPER is the upper MOSFET's total losses and PSW and PCOND are the switching and conduction losses for a given MOSFET. RDS(ON) is at the maximum junction temperature (TJ). tS is the switching period (rise or fall time) and is t2+t3 in Figure 9. = Q G × VCC × f SW (25) where QG is the total gate charge to reach VCC. Low-Side Losses Q2 switches on or off with its parallel Schottky diode conducting; therefore, VDS≈0.5V. Since PSW is proportional to VDS, Q2's switching losses are negligible and Q2 is selected based on RDS(ON) only. VDS CISS C GD C ISS Conduction losses for Q2 are given by: PCOND = (1 − D) × I OUT 2 × R DS( ON ) (26) ID QGS VSP VTH QGD 4.5V where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature and D= VOUT is the minimum duty cycle for the converter. VIN Since DMIN