ML2003CQX

www.fairchildsemi.com ML2003, ML2004 Logarithmic Gain/Attenuator Features General Description • • • • • The ML2003 and ML2004 are digitally controlled logarithmic gain/attenuators with a range of –24 to +24 dB in 0.1 dB steps. Low noise: 0 dBrnc max with +24dB gain Low harmonic distortion: -60dB max Gain range: –24 to +24dB Resolution: 0.1dB steps Flat frequency response: ±0.05dB from .3–4 kHz ±0.10dB from .1-20 kHz • Low supply current 4mA max from ±5V supplies • TTL/CMOS compatible digital interface • ML2003 has pin selectable serial or parallel interface; ML2004 serial interface only The gain settings are selected by a 9-bit digital word. The ML2003 digital interface is either parallel or serial. The ML2004 is packaged in a 14-pin DIP with a serial interface only. Absolute gain accuracy is 0.05dB max over supply tolerance of ±10% and temperature range. These CMOS logarithmic gain/attenuators are designed for a wide variety of applications in telecom, audio, sonar, or general purpose function generation. One specific intended application is analog telephone lines. Block Diagram Pin Connections GND ML2003 18-PIN DIP + + COURSE + FINE – BUFFER – VOUT – RESISTORS/ SWITCHES RESISTORS/ SWITCHES 16 16 DECODER/MODE SELECTOR C3 1 18 (LATI)C2 2 17 VCC (SID)C1 3 16 VOUT (LATO)C0 4 15 VSS PDN 5 14 A GND ATTEN/GAIN F3 6 13 VIN (SCK)F2 7 12 NC F1 8 11 F0 (SOD) GND 9 10 SER/PAR 3 2 1 20 19 TOP VIEW SER/PAR C0 (LATO) NC PDN F3 F2 (SCK) C0 C1 F0 C2 (LATI) 9-BIT LATCH & SHIFT REGISTER C1 (SID) ATTEN/ GAIN C3 F1 ML2004 14-PIN DIP 9 F2 C2 F3 F2 (SCK) NOTE: SERIAL MODE FUNCTIONS INDICATED BY PARENTHESES. C0 (LATO) F0 (SOD) ML2003 20-Pin PCC VCC VSS LATI 1 14 VCC SID 2 13 VOUT LATO 3 12 VSS PDN 4 11 A GND SCK 5 10 VIN NC 6 9 NC GND 7 8 SOD 4 18 5 6 17 16 7 15 8 14 9 10 11 12 13 VOUT VSS A GND NC NC F0 (SOD) VIN A GND C1 (SID) C2 (LATI) C3 ATTEN/GAIN VIN PDN F1 GND SER/PAR VCC TOP VIEW TOP VIEW REV. 1.1.1 3/19/01 ML2003, ML2004 PRODUCT SPECIFICATION Pin Description Name Function C3 In serial mode, pin is unused. In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND. (LATI) C2 In serial mode, input latch clock which loads the data from the shift register into the latch. In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND. (SID) C1 In serial mode, serial data input that contains serial 9 bit data word which controls the gain setting. In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND. (LATO) C0 In serial mode, output latch clock which loads the 9 bit data word back into the shift register from the latch. In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND. PDN Powerdown input. When PDN = 1, device is in powerdown mode. When PDN = 0, device is in normal operation. Pin has internal pulldown resistor to GND. F3 In serial mode, pin is unused. In parallel mode, fine gain select bit. Pin has internal pulldown resistor to GND. (SCK) F2 In serial mode, shift register clock which shifts the serial data on SID into the shift register on rising edges and out on SOD on falling edges. In parallel mode, fine gain select bit. Pin has internal pulldown resistor to GND. F1 In serial mode, pin is unused. In parallel mode, fine gain select bit. Pin has internal pulldown resistor to GND. GND Digital ground. 0 volts. All digital inputs and outputs are referenced to this ground. SER/PAR Serial or parallel select input. When SER/PAR = 1, device is in serial mode. When SER/PAR = 0, device is in parallel mode. Pin has internal pullup resistor to VCC. (SOD) F0 In serial mode, serial output data which is the output of the shift register. In parallel mode, fine gain select bit. Pin has internal pulldown resistor to GND. VIN Analog input. AGND Analog ground. 0 volts. Analog input and output are referenced to this ground. VSS Negative supply. –5 volts ±10%. VOUT Analog output. VCC Positive supply. +5 volts ±10%. ATTEN/GAIN In serial mode, pin is unused. In parallel mode, attenuation/gain select bit. Pin has internal pulldown resistor to GND. Absolute Maximum Ratings1 Parameter Max. Units Supply Voltage VCC VSS +6.5 -6.5 V V AGND with respect to GND ±0.5 V Analog Input and Output VSS –0.3V VCC +0.3 V Digital Input and Outputs GND –0.3 VCC +0.3 V Input Current Per Pin ±25 mA Power Dissipation 750 mW +150 °C 300 °C Storage Temperature Range Lead Temeperature (Soldering, 10 sec) 2 Min. -65 REV. 1.1.1 3/19/01 PRODUCT SPECIFICATION ML2003, ML2004 Operating Conditions Parameter Min. Max. Units Temperature ML2003CX, ML2004CX ML2003IX, ML2004IX 0 -40 70 85 °C °C Supply Voltage VCC VSS 4 -4 6 -6 V V Range2 Electrical Characteristics Unless otherwise specified TA = TMIN to TMAX, VCC = 5V ± 10%, VSS = -5V ±10%, Data Word: ATTEN/GAIN = 1, Other Bits = 0(0dB Ideal Gain), CL = 100pF, RL = 600Ω, SCK = LATI = LATO = 0, dBm measurements use 600Ω as reference load, digital timing measured at 1.4 V, CL = 100pF or SOD. Symbol Parameter Notes Conditions Min. Typ.3 Max. Units Analog AG Absolute gain accuracy 4 VIN=8dBm, 1 kHz -0.05 +0.05 dB RG Relative gain accuracy 4 100000001 000000000 000000001 All other gain settings All values referenced to 100000000 gain when ATTEN/GAIN = 1, VIN =8dBm when ATTEN//GAIN =0 VIN =(8dBm – Ideal Gain) in dB -0.05 -0.05 -0.05 -0.1 +0.05 +0.05 +0.05 +0.1 dB dB dB dB FR Frequency response 4 300-4000 Hz 100-20,000 Hz Relative to 1 kHz -0.05 -0.1 +0.05 +0.1 dB dB VOS Output Offset Voltage 4 VIN = 0, +24dB gain ±100 mV ICN Idle Channel Noise 4 5 VIN = 0, +24dB gain, C msg. Weighted VIN = 0, +24dB gain, 1kHz HD Harmonic Distortion 4 VIN = 8dBm gain, 1kHz Measure 2nd, 3rd harmonic relative to fundamental SD Signal to Distortion 4 VIN = 8dBm, 1 kHz C msg. weighted PSRR Power Supply Rejection 4 200mVp-p, 1 kHz sine, VIN = 0 on VCC on VSS ZIN Input impedance, VIN 4 1 Meg VINR Input Voltage Range 4 ±3.0 V VOSW Output Voltage Swing 4 ±3.0 V -6 450 0 dBrnc 900 nv/√Hz -60 +60 dB dB -60 -60 -40 -40 dB dB Digital and DC VIL Digital Input Low Voltage 4 VIH Digital Input High Voltage 4 VOL Digital Output Low Voltage 4 REV. 1.1.1 3/19/01 0.8 2.0 IOL = 2mA V V 0.4 V 3 ML2003, ML2004 PRODUCT SPECIFICATION Electrical Characteristics (continued) Unless otherwise specified TA = TMIN to TMAX, VCC = 5V ± 10%, VSS = -5V ±10%, Data Word: ATTEN/GAIN = 1, Other Bits = 0(0dB Ideal Gain), CL = 100pF, RL = 600Ω, SCK = LATI = LATO = 0, dBm measurements use 600Ω as reference load, digital timing measured at 1.4 V, CL = 100pF or SOD. Symbol Parameter Notes Conditions Min. Typ.3 Max. Units VOH Digital Output High Voltage 4 IOH = -1mA 4.0 V INS Input Current, SER/ PAR 4 VIH = GND -5 -100 µA IND Input Current, All Digital Inputs Except SER/PER 4 VIH = VCC 5 100 µA ICC VCC Supply Current 4 No output load, VIL = GND, VIH = VCC, VIN = 0 4 mA ISS VSS Supply Current 4 No output load, VIL = GND, VIH = VCC, VIN = 0 -4 mA ICCP VCC Supply Current, Powerdown Mode 4 No output load, VIL = GND, VIH = VCC 0.5 mA ISSP VSS Supply Current Powerdown Mode 4 No output load, VIL = GND, VIH = VCC -0.1 mA AC Characteristics tSET VOUT Settling Time 4 VIN = 0.185V. Change gain from –24 to +24dB. Measure from LATI rising edge to when VOUT settles to within 0.05dB of final value. 20 µs tSTEP VOUT Step Response 4 Gain = +24dB. VIN = -0.185 to +0.185V step. Measure when VOUT settles to within 0.05dB of final value. 20 µs tSCK SCK On/Off Period 4 250 ns tS SID Data Setup Time 4 50 ns tH SID Data Hold Time 4 50 ns tD SOD Data Delay 4 0 tIPW LATI Pulse Width 4 50 ns tOPW LATO Pulse Width 4 50 ns tIS, tOS LATI, LATO Setup Time 4 50 ns tIH, tOH LATI, LATO Hold Time 5 50 ns tPLD SOD Parallel Load Delay 4 0 125 125 ns ns Notes: 1. Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with respect to ground. 2. 0°C to +70°C and –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by correlation with worst-case test conditions. 3. Typicals are parametric norm at 25°C. 4. Parameter guaranteed and 100% production tested. 5. Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation. 4 REV. 1.1.1 3/19/01 PRODUCT SPECIFICATION ML2003, ML2004 Timing Diagram tSCK tSCK SCK tS tH SID tD SOD SCK tIS tIH tOS tOH LATI tIPW tOPW LATO tPLD SOD TIMING PARAMETERS ARE REFERENCED TO THE 1.4 VOLT MIDPOINT. Figure 1. Serial Mode Timing Diagram Typical Performance Curves 0 -0.5 0 -0.5 ATTEN: VIN = 0.5VRMS GAIN: VIN = 0.5VRMS/GAIN SETTING -0.10 -0.10 ATTEN: VIN = 2VRMS GAIN: VIN = 2VRMS/GAIN SETTING GAIN = +24dB AMPLITUDE (dB) AMPLITUDE (dB) GAIN = +24dB -0.15 GAIN = +18dB -0.20 GAIN = +12dB -0.25 -0.30 GAIN = +0, -24dB -0.15 -0.20 -0.25 -0.30 -0.35 -0.35 -0.40 -0.40 -0.45 -0.45 -0.50 100 1K 10K FREQUENCY (Hz) 100K Figure 2. Amplitude vs Frequency (VIN/VOUT = .5VRMS) REV. 1.1.1 3/19/01 GAIN = 0dB GAIN = –24dB -0.50 100 1K 10K FREQUENCY (Hz) 100K Figure 3. Amplitude vs Frequency (VIN/VOUT = 2VRMS) 5 ML2003, ML2004 PRODUCT SPECIFICATION Typical Performance Curves (continued) 2.0 -2 CMSG OUTPUT (NOISE) (dBmc) OUTPUT NOISE VOLTAGE (µV/√Hz) 1.8 1.6 1.4 GAIN = +24dB 1.2 GAIN = +12dB GAIN = -24dB 1 0.8 0.6 0.4 -4 -5 -6 -7 -8 -9 0.2 0 10 100 1K FREQUENCY (Hz) -10 -24 10K Figure 4. Output Noise Voltage vs Frequency 90 -18 -12 -6 -0 6 GAIN SETTING (dB) 12 18 24 Figure 5. CMSG Output Noise vs Gain Settings 0.1 ATTEN: VIN = 8dBm GAIN: VIN = 8dBm/GAIN SETTING 1KHz 0.08 0.06 GAIN ERROR (dB) 100 CMSG S/N (dB) VIN = 6 -3 80 70 60 0.04 0.02 0 -0.02 -0.04 -0.06 50 -0.08 40 -24 -18 -12 -6 -0 6 GAIN SETTING (dB) 12 18 -1.0 -24 24 Figure 6. CMSG S/N vs Gain Setting -18 -12 -6 -0 6 GAIN SETTING (dB) 12 18 24 Figure 7. Gain Error vs Gain Setting 80 80 VIN = 1kHz 70 VIN = 1kHz 70 VIN = 20kHz VIN = 20kHz S/N + D (dB) S/N + D (dB) 60 50 40 50 VIN = 50kHz 40 30 VIN = 50kHz 20 30 ATTEN: VIN = 2VRMS GAIN: VIN = 2VRMS/GAIN SETTING 10 -24 -18 -12 -6 0 6 GAIN SETTING (dB) 12 18 24 Figure 8. S/N + D vs Gain Setting (VIN/VOUT = 2VRMS) 6 60 ATTEN: VIN = 0.5VRMS GAIN: VIN = 0.5VRMS/GAIN SETTING 20 -24 -18 -12 -6 0 6 GAIN SETTING (dB) 12 18 24 Figure 9. S/N + D vs Gain Setting (VIN/VOUT = 0.5VRMS) REV. 1.1.1 3/19/01 PRODUCT SPECIFICATION ML2003, ML2004 Functional Description Powerdown Mode The ML2003 consists of a coarse gain stage, a fine gain stage, an output buffer, and a serial/parallel digital interface. A powerdown mode can be selected with pin PDN. When PDN = 1, the device is powered down. In this state, the power consumption is reduced by removing power from the analog section and forcing the analog output,VOUT, to a high impedance state. While the device is in powerdown mode, the digital section is still functional and the current data word remains stored in the latch when in serial mode. When PDN = 0, the device is in normal operation. Gain Stages The analog input, VIN, goes directly into the op amp input in the coarse gain stage. The coarse gain stage has a gain range of 0 to 22.5dB in 1.5dB steps. The fine gain stage is cascaded onto the coarse section. The fine gain stage has a gain range of 0 to 1.5dB in 0.1dB steps. In addition, both sections can be programmed for either gain or attenuation, thus doubling the effective gain range. The logarithmic steps in each gain stage are generated by placing the input signal across a resistor string of 16 series resistors. Analog switches allow the voltage to be tapped from the resistor string at 16 points. The resistors are sized such that each output voltage is at the proper logarithimic ratio relative to the input signal at the top of the string. Attenuation is implemented by using the resistor string as a simple voltage divider, and gain is implemented by using the resistor string as a feedback resistor around an internal op amp. Gain Settings Since the coarse and fine gain stages are cascaded, their gains can be summed logarithmically. Thus, any gain from –24dB to +24dB in 0.1dB steps can be obtained by combining the coarse and fine gain settings to yield the desired gain setting. The relationship between the digital select bits and the corresponding analog gain values is shown in Tables 1 and 2. Note that C3-C0 selects the coarse gain, F3-F0 selects the fine gain, and ATTEN/GAIN selects either attenuation or gain. Output Buffer The final analog stage is the output buffer. This amplifier has internal gain of 1 and is designed to drive 600 ohms and 100pF loads. Thus, it is suitable for driving a telephone hybrid circuit directly without any external amplifier. Power Supplies The digital section is powered between VCC and GND, or 5 volts. The analog section is powered between VCC and VSS and uses AGND as the reference point, or ±5 volts. GND and AGND are totally isolated inside the device to minimize coupling from the digital section into the analog section. However, AGND and GND should be tied together physically near the device and ideally close to the common power supply ground connection. Typically, the power supply rejection of VCC and VSS to the analog output is greater than –60dB at 1 kHz. If decoupling of the power supplies is still necessary in a system, VCC and VSS should be decoupled with respect to AGND. REV. 1.1.1 3/19/01 Digital Section The ML2003 can be operated with a serial or parallel interface. The SER/PAR pin selects the desired interface. When SER/PAR = 1, the serial mode is selected. When SER/PAR = 0, the parallel mode is selected. The ML2004 digital interface is serial only. Serial Mode Serial mode is selected by setting SER/PAR pin high. The serial interface allows the gain settings to be set from a serial data word. The timing for the serial mode is shown in Figure 10. The serial input data, SID, is loaded into a shift register on rising edges of the shift clock, SCK. The data can be parallel loaded into a latch when the input latch signal, LATI, is high. The LATI pulse must occur when SCK is low. In this way, a new data word can be loaded into the shift register without disturbing the existing data word in the latch. The parallel outputs of the latch control the attenuation/gain setting. The order of the data word bits in the latch is shown in Figure 11. Note that bit 0 is the first bit of the data word clocked into the shift register. Tables 1 and 2 describe how the data word programs the gain. Table 1. Fine Gain Settings (C3-C0 = 0) Ideal Gain (dB) F3 F2 F1 F0 ATTEN/GAIN = 1 ATTEN/GAIN = 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 -.1 -.2 -.3 -.4 -.5 -.6 -.7 -.8 -.9 -1.0 -1.1 -1.2 -1.3 -1.4 -1.5 0 .1 .2 .3 .4 .5 .6 .7 .8 .9 1.0 1.1 1.2 1.3 1.4 1.5 7 ML2003, ML2004 PRODUCT SPECIFICATION Table 2. Coarse Gain Settings (F3-F0 = 0) The loading and reading of the data word can be done continuously or in burst. Since the shift register and latch circuitry inside the device is static, there are no minimum frequency requirements on the clocks or data pulses. However, there is coupling (typically less than 100µV) of the digital signals into the analog section. This coupling can be minimized by clocking the data bursts in during noncritical intervals or at a frequency outside the analog frequency range. Ideal Gain (dB) C3 C2 C1 C0 ATTEN/GAIN = 1 ATTEN/GAIN = 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 -13.5 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 16.5 18.0 19.5 21.0 22.5 Parallel Mode The parallel mode is selected by setting SER/PAR pin low. The parallel interface allows the gain settings to be set with external switches or from a parallel microprocessor interface. In parallel mode, the shift register and latch are bypassed and connections are made directly to the gain select bits with external pins ATTEN/GAIN, C3-C0, and F3-F0. Tables 1 and 2 describe how these pins program the gain. The pins ATTEN/GAIN, C3-C0, and F3-F0 have internal pulldown resistors to GND. The typical value of these pulldown resistors is 100kΩ. The device also has the capability to read out the data word stored in the latch. This can be done by parallel loading the data from the latch back into the shift register when the latch signal, LATO, is high. The LATO pulse must occur when SCK is low. Then, the data word can be shifted out of the shift register serially to the output, SOD, on falling edges of the shift clock, SCK. SCK 0 1 2 3 4 5 6 7 8 SID F0 F1 F2 F3 C0 C1 C2 C3 ATT/ GAIN LATI LATO SOD a) LOAD 0 SCK 1 2 3 4 5 6 7 F1 F2 F3 C0 C1 C2 C3 8 SID LATI LATO SOD F0 ATT/ GAIN b) READ Figure 10. Serial Mode Timing 8 REV. 1.1.1 3/19/01 PRODUCT SPECIFICATION ML2003, ML2004 ATTEN/GAIN C3 C2 C1 C0 F3 F2 F1 7 6 5 4 3 2 1 8 MSB F0 FUNCTION 0 BIT NUMBER LSB Figure 11. 9-Bit Latch Applications ML2004 LOG GAIN/ATTEN ML2021 EQUALIZER VOUT VIN ML2003 VOUT VIN VOUT ATTEN/GAIN C3-C0 F3-F1 LATI SCK SID LATI SCK SID VIN 8-BIT LATCH µP µP Figure 12. Typical Serial Interface Figure 13. Typical µP Parallel Interface VIN VOUT SOD SID SOD LATI VOUT SID SOD LATI SCK SID ML2004 LATI VIN VOUT SCK VIN ML2004 SCK ML2004 µP Figure 14. Controlling Multiple ML2004 with Only 3 Digital Lines Using One Long Data Word ML2003 VIN VOUT VIN VIN A/D ATTEN/GAIN C3-C0 F3-F1 µP OR DSP 8-BIT LATCH Figure 15. AGC for DSP or Modem Front End REV. 1.1.1 3/19/01 9 ML2003, ML2004 PRODUCT SPECIFICATION ML2003 VIN ML2003 VIN VOUT ATTEN/GAIN C3-C0 F3-F1 VOUT ATTEN/GAIN C3-C0 F3-F1 UP/DOWN 8-BIT CTR +5 U/D – UP/DOWN 8-BIT COUNTER +5 COMPARATOR U/D + R2 CLOCK CLOCK R1 R3 DOWN UP R1, R2, R3 SETS AGC THRESHOLD AND HYSTERESIS FROM µP OR SWITCHES Figure 16. Analog AGC Figure 17. Digitally Controlled Volume Control ML2003 VPEAK VREF VIN VOUT VOUT ATTEN/GAIN C3-C0 F3-F1 – UP/DOWN 8-BIT COUNTER U/D COMPARATOR + CLK1 VPEAK VIN CLK2 fCLK1 DETERMINES PEAK ACQUIRE TIME fCLK2 DETERMINES PEAK HOLD TIME Figure 18. Precision Peak Detector (±1%) with Controllable Acquire and Hold Time 10 REV. 1.1.1 3/19/01 ML2003, ML2004 PRODUCT SPECIFICATION Ordering Information Part Number Temperature Range Package ML2003IQ -40°C to 85°C Molded PCC (Q20) ML2003CP 0°C to 70°C Molded DIP (P18) ML2003CQ 0°C to 70°C Molded PCC (Q20) ML2004IP -40°C to 85°C Molded DIP (P14) ML2004CP 0°C to 70°C Molded DIP (P14) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 3/19/01 0.0m 003 Stock#DS300042003 2001 Fairchild Semiconductor Corporation