ML4801

March 2001 PRELIMINARY ML4801 Variable Feedforward PFC/PWM Controller Combo GENERAL DESCRIPTION The ML4801 is a controller for power factor corrected, switched mode power supplies. Key features of this combined PFC and PWM controller are low start-up and operating currents. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC1000-2-3 specifications. The ML4801 includes circuits for the implementation of a leading edge, average current “boost” type power factor correction and a trailing edge pulse width modulator (PWM). The PFC frequency of the ML4801 is automatically set at half that of the PWM frequency generated by the internal oscillator. This technique allows the user to design with smaller output components while maintaining the optimum operating frequency for the PFC. An overvoltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brownout protection. FEATURES I I I I I Internally synchronized PFC and PWM in one IC Low start-up current (200µA typ.) Low operating current (5.5mA typ.) Low total harmonic distortion Reduces ripple current in the storage capacitor between the PFC and PWM sections Average current continuous boost leading edge PFC High efficiency trailing edge PWM optimized for current mode operation Current fed gain modulator for improved noise immunity Brown-out control, overvoltage protection, UVLO, and soft start I I I I BLOCK DIAGRAM 16 VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 8 RTCT 7 RAMP 2 9 8V VDC 6 VCC SS 5 8V 25µA 1.25V + + + 1 IEAO POWER FACTOR CORRECTOR OVP + + - 13 VCC VCC 7.5V REFERENCE S -1V + - VEA 1.6kΩ + – VREF 14 IEA 2.75V - Q GAIN MODULATOR 1.6kΩ R S Q PFC OUT Q 12 PFC ILIMIT R Q OSCILLATOR ÷2 DUTY CYCLE LIMIT PWM OUT S VFB 2.5V + Q VIN OK + 11 R DC ILIMIT Q GND 10 1.5V - PULSE WIDTH MODULATOR VCC UVLO REV. 1.1 3/9/2001 ML4801 PIN CONFIGURATION ML4801 16-Pin PDIP (P16) 16-Pin Narrow SOIC (S16N) IEAO 1 IAC 2 ISENSE 3 VRMS 4 SS 5 VDC 6 RTCT 7 RAMP 1 8 16 VEAO 15 VFB 14 VREF 13 VCC 12 PFC OUT 11 PWM OUT 10 GND 9 RAMP 2 TOP VIEW PIN DESCRIPTION PIN NAME FUNCTION PIN NAME FUNCTION 1 2 3 4 5 6 7 8 IEAO IAC I SENSE V RMS SS VDC RTCT RAMP 1 PFC transconductance current error amplifier output PFC gain control reference input 9 10 11 RAMP 2 GND PWM ramp current sense input Ground PWM OUT PWM driver output PFC OUT VCC V REF V FB VEAO PFC driver output Positive supply (connected to an internal shunt regulator). Buffered output for the internal 7.5V reference PFC transconductance voltage error amplifier input PFC transconductance voltage error amplifier output Current sense input to the PFC current limit comparator Input for PFC RMS line voltage compensation Connection point for the PWM soft start capacitor PWM voltage feedback input Connection for oscillator frequency setting components PFC ramp input 12 13 14 15 16 2 REV. 1.1 3/9/2001 ML4801 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC .............................................................................................. 18V ISENSE Voltage .................................................. -3V to 5V Voltage on Any Other Pin ...... GND - 0.3V to VCC + 0.3V I REF ........................................................................................... 20mA IAC Input Current ..................................................... 10mA Peak PFC OUT Current, Source or Sink ................. 500mA Peak PWM OUT Current, Source or Sink ............... 500mA PFC OUT, PWM OUT Energy Per Cycle ................... 1.5µJ Junction Temperature ............................................. 150°C Storage Temperature Range ...................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) ..................... 260°C Thermal Resistance (θJA) Plastic DIP ........................................................ 80°C/W Plastic SOIC ................................................... 105°C/W OPERATING CONDITIONS Temperature Range ML4801CX ................................................. 0°C to 70°C ML4801IX ............................................... -40°C to 85°C ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 15V, RT = 29.4kΩ, RRAMP1 = 15.4kΩ, CT = 270pF, CRAMP1 = 620pF, TA = Operating Temperature Range (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOLTAGE ERROR AMPLIFIER Input Voltage Range Transconductance Feedback Reference Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain PSRR CURRENT ERROR AMPLIFIER Input Voltage Range Transconductance Input Offset Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain PSRR 11V < VCC < 16.5V ∆VIN = ± 0.5V, VOUT = 6V ∆VIN = ± 0.5V, VOUT = 1.5V -40 40 55 60 6.0 VNON INV = VINV, VEAO = 3.75V -1.5 60 0 100 8 -0.5 6.7 0.65 -70 70 65 75 1.0 -150 150 2 120 15 -1.0 V µ 11V < VCC < 16.5V ∆VIN = ± 0.5V, VOUT = 6V ∆VIN = ± 0.5V, VOUT = 1.5V -40 40 60 60 Note 2 6.0 VNON INV = VINV, VEAO = 3.75V 0 40 2.43 65 2.50 -0.5 6.7 0.1 -70 70 70 70 0.4 -150 150 5 80 2.57 -1.0 V V µA V V µA µA dB dB mV µA V V µA µA dB dB REV. 1.1 3/9/2001 Ω µ Ω 3 ML4801 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL OVP COMPARATOR Threshold Voltage Hysteresis PFC ILIMIT COMPARATOR Threshold Voltage ∆PFC ILIMIT Threshold - Gain Modulator Output PARAMETER CONDITIONS MIN TYP MAX UNITS 2.65 175 2.75 250 2.85 325 V mV -0.9 120 -1.0 220 150 -1.1 V mV Delay to Output DC ILIMIT COMPARATOR Threshold Voltage Input Bias Current Delay to Output VIN OK COMPARATOR Threshold Voltage Hysteresis GAIN MODULATOR Gain (Note 3) IAC = 100µA, VRMS = VFB = 0V IAC = 50µA, VRMS = 1V, VFB = 0V IAC = 50µA, VRMS = 1.8V, VFB = 0V IAC = 100µA, VRMS = 3.3V, VFB = 0V Bandwidth Output Voltage OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Voltage PFC Dead Time CT Discharge Current VRAMP 2 = 0V, VRAMP 1 = 2.5V 350 3.5 Over Line and Temp 182 TA = 25ºC 11V < VCC < 16.5V 188 IAC = 100µA IAC = 350µA, VRMS = 1V, VFB = 0V 0.65 0.65 1.90 0.90 0.20 2.4 0.8 1.4 300 ns 1.5 ± 0.3 150 1.6 ±1 300 V µA ns 2.5 1.0 2.6 1.2 V V 0.85 2.20 1.05 0.30 10 0.75 1.05 2.40 1.25 0.40 MHz 0.85 V 200 1 2 212 kHz % % 218 2.5 470 5.5 600 7.5 kHz V ns mA 4 REV. 1.1 3/9/2001 ML4801 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL REFERENCE Output Voltage Line Regulation Load Regulation Temperature Stability Total Variation Long Term Stability PFC Minimum Duty Cycle Maximum Duty Cycle Output Low Voltage VIEAO > 6.7V VIEAO < 1.2V IOUT = -20mA IOUT = -100mA IOUT = -10mA, VCC = 9V Output High Voltage IOUT = 20mA IOUT = 100mA Rise/Fall Time PWM DC VOL Duty Cycle Range Output Low Voltage IOUT = -20mA IOUT = -100mA IOUT = -10mA, VCC = 9V VOH Output High Voltage IOUT = 20mA IOUT = 100mA Rise/Fall Time SUPPLY Start-up Current Operating Current Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: Includes all bias currents to other circuits connected to the VFB pin. Note 3: Gain = K x 5.3V; K = (IMULO - IOFFSET) x IAC x (VEAO - 0.625V)-1. PARAMETER CONDITIONS MIN TYP MAX UNITS TA = 25ºC, I(VREF) = 1mA 11V < VCC < 16.5V 1mA < I(VREF) < 10mA 7.4 7.5 10 10 0.4 7.6 25 20 V mV mV % Line, Load, Temp TJ = 125ºC, 1000 Hours 7.35 5 7.65 25 V mV 0 90 95 0.4 0.7 0.4 VCC - 0.8 VCC - 2.0 50 0.8 2.0 0.8 % % V V V V V ns CL = 1000pF 0-44 0-47 0.4 0.7 0.4 0-50 0.8 2.0 0.8 % V V V V V VCC - 0. 8 VCC - 2.0 50 CL = 1000pF ns VCC = 12V, CL = 0 VCC = 14V, CL = 0 12.4 2.7 200 5.5 13.0 3.0 350 7.0 13.6 3.3 µA mA V V REV. 1.1 3/9/2001 5 ML4801 FUNCTIONAL DESCRIPTION The ML4801 consists of a combined average-currentcontrolled, continuous boost Power Factor Corrector (PFC) front end and a synchronized Pulse Width Modulator (PWM) back end. It is distinguished from earlier combo controllers by its dramatically reduced start-up and operating currents. The PWM section is intended to be used in current mode. The PWM stage uses conventional trailing-edge duty cycle modulation, while the PFC uses leading-edge modulation. This patented leading/trailing edge modulation technique results in a higher useable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC buss capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the reduced ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the ML4801 runs at twice the frequency of the PFC, which allows the use of smaller PWM output magnetics and filter capacitors while holding down the losses in the PFC stage power components. In addition to power factor correction, a number of protection features have been built into the ML4801. These include soft-start, PFC over-voltage protection, peak current limiting, brown-out protection, duty cycle limit, and under-voltage lockout. POWER FACTOR CORRECTION Power factor correction makes a non-linear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with, and proportional to, the line voltage, so the power factor is unity (one). A common class of non-linear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peakcharging effect which occurs on the input filter capacitor in such a supply causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such a supply presents a power factor to the line of less than one (another way to state this is that it causes significant current harmonics to appear at its input). If the input current drawn by such a supply (or any other non-linear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved. To maintain the input current of a device drawing power from the AC line in phase with, and proportional to, the input voltage, a way must be found to cause that device to load the line in proportion to the instantaneous line voltage. The PFC section of the ML4801 uses a boostmode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges, at twice line frequency, from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current which the converter draws from the power line matches the instantaneous line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VACrms. The other condition is that the current which the converter is allowed to draw from the line at any given instant must be proportional to the line voltage. The first of these requirements is satisfied by establishing a suitable voltage control loop for the converter, which sets an average operating level for a current error amplifier and switching output driver. The second requirement is met by using the rectified AC line voltage to modulate the instantaneous input of the current control loop. Such modulation causes the current error amplifier to command a power stage current which varies directly with the input voltage. In order to prevent ripple which will necessarily appear at the output of the boost circuit (typically about 10VAC on a 385V DC level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input voltage varies. Since the boost converter topology in the ML4801 PFC is of the current-averaging type, no slope compensation is required. PFC SECTION Gain Modulator Figure 1 shows a block diagram of the PFC section of the ML4801. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltage. There are three inputs to the gain modulator. These are: 1) A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC. The rectified AC input sine wave is converted to a proportional current via an (external) resistor and is then fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. 2) A voltage proportional to the long-term rms AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The gain modulator’s output is 6 REV. 1.1 3/9/2001 ML4801 FUNCTIONAL DESCRIPTION 16 VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 8 RTCT 7 DUTY CYCLE LIMIT OSCILLATOR ÷2 GAIN MODULATOR 1.6kΩ + (Continued) 1 13 POWER FACTOR CORRECTOR OVP + - IEAO VCC 7.5V REFERENCE VREF 14 VEA 1.6kΩ + – IEA 2.75V PFC CONTROLLER 8V PFC ILIMIT -1V + - PFC OUTPUT DRIVER PFC OUT 12 Figure 1. PFC Section Block Diagram inversely proportional to VRMS2 (except at unusually low values of VRMS where special gain contouring takes over to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between VRMS and gain is designated as K. 3) The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage. The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual-ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line. The general form for the output of the gain modulator is: IGAINMOD = IAC ´ VEAO VRMS 2 ´ 1V Current Error Amplifier The current error amplifier’s output controls the PFC duty cycle to keep the current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the ISENSE pin (current into ISENSE ≅ VSENSE/1.6kΩ). The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. In higher power applications, two current transformers are sometimes used, one to monitor the ID of the boost MOSFET(s) and one to monitor the IF of the boost diode. As stated above, the inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator’s output decreases, the output duty cycle will decrease to achieve a less negative voltage on the ISENSE pin. Cycle-By-Cycle Current Limiter The ISENSE pin, as well as being a part of the current feedback loop, is a direct input to the cycle-by-cycle current limiter for the PFC section. Should the input voltage at this pin ever be more negative than -1V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle. 7 More exactly, the output current of the gain modulator is More exactly, the output current of the gain modulator is given by: given by: IGAINMOD = K × (VEAO − 0.625V) × IAC (1) (1) where K is in units of V-1. Note that the output current of the gain modulator is limited to ≅ 500µA. REV. 1.1 3/9/2001 ML4801 FUNCTIONAL DESCRIPTION Overvoltage Protection Overvoltage Protection The OVP comparator serves to protect the power circuit The OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load from being subjected to excessive voltages if the load should suddenly change. A resistor divider from the high should suddenly change. A resistor divider from the high voltage DC output of the PFC is fed to VFB.. When the voltage DC output of the PFC is fed to VFB When the voltage on VFB exceeds 2.75V, the PFC output driver is voltage VFB exceeds 2.75V, the PFC output driver is shut down. The PWM section will continue to operate. The The PWM section The OVP comparator has 250mV of hysteresis, and the PFC OVP comparator has 250mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.5V. will not restart until the voltage at VFB drops below 2.5V. The OVP trip level should be set at a level where the The OVP trip level should be set at a level where the active and passive external power components and the active and passive external power components and the ML4801 are within their safe operating voltages, but not so low as to interfere with the regulator operation of the low as to interfere with the regulator operation boost voltage regulation loop. boost voltage regulation loop. Error Amplifier Compensation Error Amplifier Compensation The PWM loading of the PFC can be modeled as a The PWM loading of the PFC can be modeled as a negative resistor; an increase in input voltage to the PWM causes a decrease in the input current. This response causes a decrease in the input current. This response dictates the proper compensation of the two dictates the proper compensation of the two transconductance error amplifiers. Figure 2 shows the transconductance error amplifiers. Figure 2 shows the types of compensation networks most commonly used for types of compensation networks most commonly used for the voltage and current error amplifiers, along with their voltage and current error amplifiers, along with their respective return points. The current loop compensation is respective The current loop compensation returned to VREF tto produce a soft-start characteristic on returned to VREF o produce a soft-start characteristic on the PFC: as the reference voltage comes up from zero the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on IEAO which volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty prevents the PFC from immediately demanding a full duty cycle on its boost converter. cycle on its converter. There are two major concerns when compensating the There are two major concerns when compensating the voltage loop error amplifier; stability and transient voltage loop error amplifier; stability and transient response. Optimizing interaction between transient response. Optimizing interaction between transient response and stability requires that the error amplifier’s response and stability requires that the error amplifier ’s open-loop crossover frequency should be 1/2 that of the crossover frequency should be 1/2 that of the line frequency, or 23Hz for a 47Hz line (lowest frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). Rapid anticipated international power frequency). Rapid perturbations in line or load conditions will cause the perturbations in line or load conditions will cause the input to the voltage error amplifier (VFB)) to deviate from the voltage error amplifier (VFB to deviate from its 2.5V (nominal) value. If this happens, the its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier will amplifier increase significantly. This increases the gain-bandwidth This increases the gain-bandwidth product of the voltage loop, resulting in a much more product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristic. The current amplifier compensation is characteristic. The current amplifier compensation is similar to that of the voltage error amplifier with the that of the voltage error amplifier with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7kHz for a 100kHz switching frequency. There is a also a degree of gain contouring applied to the There is a also a degree of gain contouring applied to the transfer characteristic of the current error amplifier, to transfer characteristic of the current error amplifier, to increase its speed of response to current-loop its speed of response to current-loop perturbations. However, the boost inductor will usually be However, the boost inductor (Continued) the dominant factor in overall current loop response. dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than Therefore, this contouring is significantly less that of the voltage error amplifier. that of the voltage error amplifier. For more information on compensating the current and For more information on compensating the current and voltage control loops, see Application Notes 33, 34, and voltage control loops, see Application Notes 33, 34, and 55. Application Note 16 also contains valuable Application Note 16 also contains valuable information for the design of this class of PFC. Oscillator (RTCT) Oscillator (RTCT) The oscillator frequency is set by the values of RT and CT,, The oscillator frequency is set by the values of RT and CT which determine the ramp and off-time of the ML4801's master oscillator: oscillator: fOSC = 1 t RAMP + t DEADTIME (2) The deadtime of the oscillator is derived from the The deadtime of the oscillator derived from following equation: equation: t RAMP = C T ´ R T ´ ln at VREF = 7.5V: VREF = FG V HV REF REF - 125 . . - 375 IJ K (3) t RAMP = C T ´ R T ´ 0.51 The ramp of the oscillator may be determined using: The ramp of the oscillator may be determined using: t DEADTIME = 25V . ´ C T = 455 ´ C T 55mA . (4) The deadtime is so small (tRAMP >> ttDEADTIME)) that the The deadtime is so small (tRAMP >> DEADTIME that the GND GND VREF VREF PFC PFC OUTPUT OUTPUT VEAO VEAO VFB VFB 2.5V 2.5V IIAC AC VRMS VRMS IISENSE SENSE VEA VEA -+ + 16 16 IEAO IEAO 1 1 15 15 IEA IEA + + -- + + -- 2 2 4 4 3 3 GAIN GAIN MODULATOR MODULATOR Figure 2. Compensation Network Connections for the Figure 2. Compensation Network Connections for the Voltage and Current Error Amplifiers Voltage and Current Error Amplifiers REV. 1.1 3/9/2001 8 ML4801 FUNCTIONAL DESCRIPTION fOSC = 1 t RAMP (Continued) operating frequency can typically be approximated by: typically be approximated by: (5) (5) by a current sensing This voltage may be derived either by a current sensing resistor or a current transformer. Soft Start Soft Start Start-up of the PWM is controlled by the selection of the Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 25µA 25µA supplies the charging current for the capacitor, and startup of the PWM begins at 1.25V. Start-up delay can be up of the PWM begins at 1.25V. Start-up delay can be programmed by the following equation: programmed by the following equation: C SS = t DELAY × 25µA . 125V EXAMPLE: EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at: fOSC = 100kHz = 1 t RAMP -5 t RAMP = 0.51 ´ R T ´ C T = 1 ´ 10 (6) (6) Solving for RT x CT yields 2 x 10-4. Selecting standard Solving for RT x CT yields 2 x 10-4. Selecting standard components values, CT = 270pF, and RT = 36.5kΩ. components values, CT = 270pF, and RT = 36.5kΩ. PWM SECTION PWM SECTION The PWM section of the ML4801 is straightforward, but there are several points which should be noted. Foremost there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC among these is its inherent synchronization to the PFC section of the device, and that the PWM stage is section of the device, and that the PWM stage is optimized for current-mode operation. In the ML4801, the optimized for current-mode operation. In the ML4801, the operating frequency of the PFC section is fixed at 1/2 of the PWM's operating frequency. This is done through the use of a 2:1 digital frequency divider ("T" flip-flop) linking use of a 2:1 digital frequency divider ("T" flip-flop) linking the two functional sections of the IC. the two functional sections of the IC. No voltage error amplifier is included in the PWM stage No voltage error amplifier is included in the PWM stage of the ML4801, as this function is generally performed on the output side of the PWM’s isolation boundary. To facilitate the design of optocoupler feedback circuitry, an facilitate the design of optocoupler feedback circuitry, an offset has been built into the PWM’s RAMP 2 input which offset has been built into the PWM’s RAMP 2 input which allows VDC to command a zero percent duty cycle for allows VDC to command a zero percent duty cycle for input voltages below 1.25V. input voltages below 1.25V. PWM Current Limit PWM Current Limit The RAMP 2 pin provides a direct input to the cycle-byThe RAMP 2 pin provides a direct input to the cycle-bycycle current limiter for the PWM section. Should the cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1.5V, the output of input voltage at this pin ever exceed 1.5V, the output of the PWM will be disabled until the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. cycle. VIN OK Comparator VIN OK Comparator The VIN OK comparator monitors the DC output of the VIN OK PFC and inhibits the PWM if this voltage on VFB is less FB than its nominal 2.5V. Once this voltage reaches 2.5V, than its nominal 2.5V. Once this voltage reaches 2.5V, which corresponds to the PFC output capacitor being which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start charged to its rated boost voltage, the soft-start commences. PWM Control (RAMP 2) PWM Control (RAMP 2) In addition to its PWM current limit function, RAMP 2 is In addition to its PWM current limit function, RAMP 2 is used as the sampling point for a voltage representing the used as the sampling point for a voltage representing the current in the primary of the PWM’s output transformer. where CSS is the required soft start capacitance, and where CSS is the required soft start capacitance, and tDELAY is the desired start-up delay. tDELAY is the desired start-up delay. It is important that the time constant of the PWM soft-start It is important that the time constant of the PWM soft-start allow the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms. least 5ms. Solving for the minimum value of CSS: Solving for the minimum value of CSS: C SS = 5ms × 25µA = 100nF 125V . Generating VCC Generating VCC The ML4801 is a voltage-fed part. It requires an external The ML4801 is a voltage-fed part. It requires an external 15V±10% 15V± 10% or better Zener shunt voltage regulator, or some other VCC regulator, to maintain the voltage supplied to CC the part at 15V nominal. This allows a low power the part at 15V nominal. This allows a low power dissipation while at the same time delivering 13V dissipation while at the same time delivering 13V nominal of gate drive at the PWM OUT and PFC OUT nominal of gate drive at the PWM OUT and PFC OUT outputs. If using a Zener diode, it is important to limit the outputs. If using a Zener diode, it is important to limit the current through the Zener to avoid overheating or destroying it. This can be easily done with a single resistor This in series with the Vcc pin, returned to a bias supply of in series with the Vcc pin, returned to a bias supply of typically 18V to 20V. The resistor’s value must be chosen typically 18V to 20V. The resistor’s value must be chosen to meet the operating current requirement of the ML4801 to meet the operating current requirement of the ML4801 itself (8.5mA max.) plus the current required by the two itself (8.5mA max.) plus the current required by the two gate driver outputs. EXAMPLE: EXAMPLE: With a VBIAS of 20V, a VCC limit of 16.5V (max) and With a VBIAS of 20V, a VCC limit of 16.5V (max) and driving a total gate charge of 110nC at 100kHz (1 IRF840 driving a total gate charge of 110nC at 100kHz (1 IRF840 MOSFET and 2 IRF830 MOSFETs), the gate driver current required is: IGATEDRIVE = 100kHz ´ 110nC = 11 mA RBIAS = 20V - 16.5V = 180Ω mA 7.5mA + 11 The ML4801 should be locally bypassed with a 10nF and a 1µF ceramic capacitor. In most applications, an a 1µF ceramic capacitor. In most applications, an electrolytic capacitor of between 33µF and 100µF is also electrolytic capacitor of between 33µF and 100µF is also required across the part, both for filtering and as part of required across the part, both for filtering and as part of the start-up bootstrap circuitry. REV. 1.1 3/9/2001 9 ML4801 LEADING/TRAILING MODULATION Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure 3 shows a typical trailing edge control scheme. In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 4 shows a leading edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary “no-load” period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC’s output ripple voltage can be reduced by as much as 30% using this method. TYPICAL APPLICATIONS Figure 9 is the application circuit for a complete 100W power factor corrected power supply, designed using the methods and general topology detailed in Application Note 33. L1 + DC I1 VIN SW2 I2 I3 I4 RL + DC L1 I1 VIN SW2 I2 I3 I4 SW1 C1 RAMP SW1 C1 RL RAMP VEAO REF U3 + –EA DFF RAMP OSC U4 CLK + – U1 R Q D U2 Q CLK VSW1 RAMP OSC U4 CLK U3 + –EA VEAO TIME REF VEAO + – CMP U1 DFF VSW1 R Q D U2 Q CLK TIME TIME TIME Figure 3. Typical Trailing Edge Control Scheme Figure 4. Leading/Trailing Edge Control Scheme 10 REV. 1.1 3/9/2001 ML4801 160 180 IVEAO (µA) 0 90 –160 0 0 1 2 VFB (V) 3 4 5 0 1 2 VFB (V) 3 4 5 Figure 5. IVEAO vs. VFB Figure 6. gM of VOTA 200 500 160 120 80 40 0 K 0 0 1 2 VFB (V) 3 4 5 0 1 2 3 4 5 VRMS (V) Figure 7. gM of IOTA Figure 8. K of Multiplier REV. 1.1 3/9/2001 11 ML4801 AC INPUT 85 TO 265VAC C1 680nF F1 3.15A L1 3mH Q1 IRF840 R2A 357kΩ R1A 249kΩ R27 82kΩ R2B 357kΩ 15V C3 100nF R21 22Ω C4 C5 10nF 100µF C25 100nF T1 R30 4.7kΩ R15 3Ω D6 BYV26C D1 8A, 600V "FRED " Diode Q2 R17 IRF830 33Ω D5 BYV26C D7 16V T2 L2 D11 MBR2545CT 15µH C24 1µF 12VDC BR1 4A, 600V C21 1800µF R28 180Ω D3 BYV26C C20 1µF RTN R24 1.2kΩ R1B 249kΩ R3 75kΩ C30 47µF C12 20µF 1N4745 16V R7A 178kΩ R14 33Ω Q3 IRF830 R23 1.5kΩ R20 1.5Ω 10kΩ C22 4.7µF R18 220Ω R22 8.66kΩ D12 1N5401 D13 1N5401 C7 220pF R12 27kΩ C6 1µF R7B 178kΩ R19 220Ω C23 R26 100nF 10kΩ R25 2.26kΩ C2 470nF R4 13kΩ TL431 IEAO IAC ISENSE R5 300mΩ 1W VDC VFB VREF VCC PFC OUT PWM OUT GND RAMP 2 D8 1N5818 D10 1N5818 C15 10nF C16 1µF C13 100nF C14 1µF R8 2.37kΩ C31 1nF R11 768kΩ C8 100nF C9 10nF VRMS SS VDC C19 220nF RTCT 60kΩ RAMP 1 ML4801 1nF C18 270pF R6 36.5kΩ 20kΩ R10 6.2kΩ C17 220pF L1: Premier Magnetics #TSD-734 L2: 15µH, 10A DC T1: Premier Magnetics #PMGD- 03 T2: Premier Magnetics #TSD-1048 Premier Magnetics: (714) 362-4211 C11 10nF 470pF Figure 9. 100W Power Factor Corrected Power Supply 12 REV. 1.1 3/9/2001 ML4801 PHYSICAL DIMENSIONS inches (millimeters) Package: P16 16-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 16 PIN 1 ID 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) 0.02 MIN (0.50 MIN) (4 PLACES) 1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.022 (0.40 - 0.56) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S16N 16-Pin Narrow SOIC 0.386 - 0.396 (9.80 - 10.06) 16 PIN 1 ID 0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20) 1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0º - 8º 0.055 - 0.061 (1.40 - 1.55) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.004 - 0.010 (0.10 - 0.26) 0.015 - 0.035 (0.38 - 0.89) 0.006 - 0.010 (0.15 - 0.26) REV. 1.1 3/9/2001 13 ML4801 ORDERING INFORMATION PART NUMBER ML4801CP ML4801CS ML4801IP ML4801IS TEMPERATURE RANGE 0°C to 70°C 0°C to 70°C –40°C to 85°C –40°C to 85°C PACKAGE 16-Pin Plastic DIP (P16) 16-Pin Narrow SOIC (S16N) 16-Pin Plastic DIP (P16) 16-Pin Narrow SOIC (S16N) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2000 Fairchild Semiconductor Corporation REV. 1.1 3/9/2001 14