ML6553

www.fairchildsemi.com ML6553 Bus Termination Regulator Features • Can source and sink up to 1A • Generates termination voltages for DDR SDRAM, SSTL_2 SDRAM, SGRAM, or equivalent memories • Generates termination voltages for active termination schemes for GTL+, DDR, Rambus™, VME, LV-TTL, PECL and other high speed logic • VL regulated to within 3% at 800mA • Minimum external components. Requires no feedback compensation • Fixed frequency operation for easier system integration • Lower power consumption than passive, resistor divider termination, reducing heat by as much as 50% • Separate voltages for VCCQ and PVDD General Description The ML6553 switching regulator is designed to convert voltage supplies ranging from 2.0V to 3.6V into a desired output voltage or termination voltage for various applications. The ML6553 can be implemented to produce regulated output voltages in two different modes. In the default mode, the output is 50% of voltage applied to VCCQ. The switching regulator is capable of sourcing or sinking up to 1A of current. The ML6553, used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. The voltage output of the regulator can be used as a termination voltage for other bus interface standards such as SSTL, DDR, Rambus™, GTL+, VME, LV-CMOS, LV-TTL, P-ECL, and CMOS. Block Diagram 1 VCCQ 4 AVCC CLK OSCILLATOR/ RAMP GENERATOR BUFFER RAMP S – R + + 190kΩ – VINTEG + PWM COMPARATOR Q Q 5 PVDD VL Q1 VL 7 Q2 DGND 8 6 190kΩ VCCQ/2 2 – AGND 3 REV. 1.0.2 3/21/01 ML6553 PRODUCT SPECIFICATION Pin Configuration ML6553 8-Pin SOIC (S08) VCCQ VCCQ/2 AGND AVCC 1 2 3 4 8 7 6 5 DGND VL VL PVDD TOP VIEW Pin Description Pin 1 2 3 4 5 6 7 8 Name VCCQ VCCQ/2 AGND AVCC PVDD VL VL DGND VREF output is VCCQ/2 Analog signal ground Voltage supply for the noise sensitive analog control section. Voltage supply for the internal power transistors. Output inductor connection Output inductor connection Return for the internal power transistors. Function Voltage supply for internal reference voltage divider Absolute Maximum Ratings Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter VIN Voltage on Any Other Pin Peak Switch Current (IPEAK) Average Switch Current (IAVG) Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance (θJA) Output Current, Source or Sink –65 GND – 0.3 Min. Max. 5 VIN + 0.3 1 300 150 150 150 160 1 Unit V V A mA °C °C °C °C/W A Operating Conditions Temperature Range AVCC, PVDD Operating Range 0°C to 70°C 2.0V to 3.6V 2 REV. 1.0.2 3/21/01 PRODUCT SPECIFICATION ML6553 Electrical Characteristics AVCC = PVDD = 3.3V ±10%. Unless otherwise specified, TA = Operating Temperature Range (Note 1) Symbol VTT Parameter Output Voltage, VTT (See Figure 2) IOUT = 0, VREF = open IOUT = ±1A, VREF = open Note 2 VCCQ/2 Output Voltage, VCCQ/2 Conditions VCCQ = 2.3V VCCQ = 2.5V VCCQ = 2.7V VCCQ = 2.3V VCCQ = 2.5V VCCQ = 2.7V Min 1.12 1.22 1.32 1.09 1.19 1.28 Typ 1.15 1.25 1.35 1.15 1.25 1.35 Max Units 1.18 1.28 1.38 1.21 1.31 1.42 V V V V V V V V V mΩ kHz mA Switching Regulator VCCQ = 2.3V 1.139 VCCQ = 2.7V 1.337 1.15 1.162 1.35 1.364 20 650 3 VCCQ = 2.5V 1.238 1.25 1.263 Source Resistance from VL Switching Frequency IREF Supply IQ Quiescent Current IOUT = 0, no load IVCCQ IAVCC IPVDD 500 4.5 10 Output Load Current for VCCQ/2 Pin µA µA mA Notes: 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 2. Specifications are taken from the application circuit in Figure 2 using the recommended component values. REV. 1.0.2 3/21/01 3 ML6553 PRODUCT SPECIFICATION Functional Description The ML6553 switching regulator is designed to sink and source 1A load current and maintain a tight output voltage regulation without the need for external feedback. Feedback is accomplished internally by setting the average value of VL equal to VCCQ/2 through a high gain error amp. The ML6553 implements an open loop design that does not require external loop compensation, providing a simplified regulator design that can be used in cost sensitive applications. on and the low side switch (Q2) is held off. In this state, the voltage at VL is pulled up to PVDD, which the error amp, integrates and inverts. The resulting output voltage of the error amp will decline until it intersects the rising voltage of the ramp. When this occurs the flip-flop is reset. In the reset state, the high side switch is off, the low side switch is on and VL is pulled to DGND. The flip-flop will remain in the reset state until the next clock pulse. A timing diagram is shown in Figure 1. In the absence of a load, the duty cycle will be 50% if the PVDD and VCCQ are the same. The average voltage at VL will be half the voltage applied to VCCQ, and the net current change will be zero. If the ML6553 needs to source current, the duty cycle will increase, resulting in more current being supplied to the load. If the ML6553 needs to sink current, the duty will decrease, resulting in current being pulled from the load and returned back to the PVDD supply. Regulator Operation Refer to the block diagram on the first page of this datasheet. The oscillator/ramp block generates a 650kHz clock pulse that is used to set the flip-flop. It also generates a 650kHz ramp that the PWM comparator uses to reset the flip-flop. When the flip-flop is set, the high side switch (Q1) is turned VL RAMP VINTEG PWMCMP CLK Q Figure 1. Timing Diagram 4 REV. 1.0.2 3/21/01 PRODUCT SPECIFICATION ML6553 Design Consideration Inductor Selection The ML6553 requires the selection of an external inductor. A value of 4.7µH is a good choice, but any value between 2.2µH and 10µH is acceptable. Choosing an inductance value of less than 2.2µH will reduce the component’s footprint or the DC resistance, but the output voltage ripple will increase. Conversely, inductance values greater than 10µH will reduce the output ripple, but component size and output regulation become issues. It is important to use an inductor that is rated to handle 1.5A peak currents without saturating. Also look for an inductor with low winding resistance. An inductor with low winding resistance leads to better regulation and higher output current capability. A good rule of thumb is to use inductors with 20mΩ or less of winding resistance. The final selection of the inductor will be based on trade-offs between size, cost and performance. Make your selections carefully. Inductor tolerance, core and copper loss will vary with the type of inductor selected and should be evaluated with the ML6553 under worst case conditions to determine its suitability. Suggested inductor for L1: DC Inductance Resistance Input Capacitor It is recommended to de-couple the PVDD input with a 47µF to 100µF capacitor. This provides the benefits of preventing the input ripple from affecting the ML6553 control circuitry, as well as improves the efficiency by reducing the I squared R losses during the charge cycle of the inductor. Again, a low ESR capacitor (such as tantalum) is recommended. The AVCC input should be de-coupled with at least a ceramic capacitor but a low pass RC filter is recommended if the supply is particularly noisy. If a RC filter is used, the series resistor value needs to low enough to prevent excessive voltage drops and high enough to provide effective filtering. Resistor values on the order of 100Ω are acceptable. The VCCQ pin can also be bypassed with a ceramic capacitor if noise is present. The VCCQ pin can be de-coupled with a low pass RC filter if there is significant noise pickup on its input. If a RC filter is used, resistor values on the order of 1,000Ω are acceptable. Layout Good layout practices will ensure the proper operation of the ML6553. Some layout guidelines follow: • Use adequate ground and power traces or planes. • Keep the 47µF-100µF input capacitor as close to PVDD and DGND as possible. • Use short trace lengths from the inductor to the VL pins and from the inductor to the output capacitors. • Use a separate trace from AGND to DGND, and use DGND as the ground point for all the power components. • Use additional bypass capacitors at each termination resistor pack. A typical application circuit schematic is shown in Figure 2, and a sample layout is shown in Figure 3. ( DESIRED OVA – OUTPUT OVA ) × V TT I OUT ( MAX ) = ------------------------------------------------------------------------------------------------------L DCR + 0.020 Manufacturer Part No. Coiltronics Coiltronics UP3-4R7 (561) 241-7876 4.7µH 0.011Ω Output Capacitor The output capacitor filters the pulses of current from the bus terminator regulator as well as lowers the AC output impedance. For the best performance, one 330µF OS-CON decoupling capacitor is recommended. Note that data transitions on the bus cause fast changes in output current. These fast current changes cause high frequency spikes to appear on the output. To minimize these effects, choose an output capacitor with a combined ESR of less than 50mΩ and use good layout practices to minimize trace inductance from the output capacitors to the termination resistors. In addition, it is also recommended to bypass the termination resistors with 0.01µF ceramic capacitors. Suitable capacitors can be obtained from the following vendors: AVX Sanyo (207) 282-5111 (619) 661-6835 TPS Series OS-CON Series (1) Where LDCR is the DC resistance of the output inductor, L1 in Figure 2, and 0.020 is the source resistance of the output VL. Both LDCR and 0.020 are in Ohms. REV. 1.0.2 3/21/01 5 ML6553 PRODUCT SPECIFICATION Output Current Capability The maximum current available at the output of the regulator is related to the DC resistance of the inductor, the source impedance of the ML6553, and the desired regulation. The source impedance of the ML6553 can be estimated at 20mΩ with an initial output voltage accuracy of ±1%. So the maximum output current can be estimated using: ( DESIRED OVA – INITIAL OVA ) I OUT ( MAX ) ≈ ----------------------------------------------------------------------------------- × V TT L DCR + 0.020 This is enough current capability to terminate 50 bus lines, assuming 16mA of drive current per line. Since the feedback loop is closed internally on the ML6553 the total series resistance of the L/C output filter contributes to increased deviation from no load to full load. The output source impedance of the ML6553 is approximately 20mΩ. A 1A load current yields 11mV (from L1) in output deviation +20mV from the ML6553. Be sure to factor in the component ESR values when constrained to a particular maximum output deviation. Adequately bypass the VTT output with SMD film capacitors to reduce transients generated by stray lead inductance. So, for an inductor with 11mΩ DC resistance, a termination voltage of 1.25V, and a desired output voltage accuracy of 3%: ( 3% – 1% ) × 1.25 I OUT ( MAX ) = -------------------------------------------------------- = 0.806A ( 0.011 + 0.020 ) × 100 (2) VCCQ 2.5V VCCQ/2 R1 1kΩ PVDD 3.3V GND C1 0.1µF C2 0.1µF R2 100Ω U1 1 DGND VCCQ 2 VL VCCQ/2 3 VL AGND 4 PVDD AVCC ML6553 8 7 6 5 L1 4.7µH VTT C5 330µF OS-CON C6 0.1µF C3 0.1µF C4 100µF Figure 2. Application Schematic Figure 3. ML6553 Board Layout 6 REV. 1.0.2 3/21/01 ML6553 PRODUCT SPECIFICATION Mechanical Dimensions Inches (Millimeters) S08 8-Pin SOIC 0.189 - 0.199 (4.80 - 5.06) 8 PIN 1 ID 0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20) 1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0º - 8º 0.055 - 0.061 (1.40 - 1.55) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.004 - 0.010 (0.10 - 0.26) 0.015 - 0.035 (0.38 - 0.89) 0.006 - 0.010 (0.15 - 0.26) Ordering Information Part Number ML6553CS-1 Temperature Range 0°C to 70°C Package 8-Pin SOIC (S08) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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