MM74C02

MM74C00 • MM74C02 • MM74C04 Quad 2-Input NAND Gate • Quad 2-Input NOR Gate • Hex Inverter October 1987 Revised January 1999 MM74C00 • MM74C02 • MM74C04 Quad 2-Input NAND Gate • Quad 2-Input NOR Gate • Hex Inverter General Description The MM74C00, MM74C02, and MM74C04 logic gates employ complementary MOS (CMOS) to achieve wide power supply operating range, low power consumption, high noise immunity and symmetric controlled rise and fall times. With features such as this the 74C logic family is close to ideal for use in digital systems. Function and pin out compatibility with series 74 devices minimizes design time for those designers already familiar with the standard 74 logic family. All inputs are protected from damage due to static discharge by diode clamps to VCC and GND. Features s Wide supply voltage range: s Guaranteed noise margin: s High noise immunity: s Low power consumption: Fan out of 2 driving 74L 3V to 15V 1V 10 nW/package (typ.) 0.45 VCC (typ.) s Low power: TTL compatibility: Ordering Code: Order Number MM74C00M MM74C00N MM74C02N MM74C04M MM74C04N Package Number M14A N14A M14A M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP and SOIC MM74C00 MM74C02 Top View MM74C04 Top View Top View © 1999 Fairchild Semiconductor Corporation DS005877.prf www.fairchildsemi.com MM74C00 • MM74C02 • MM74C04 Absolute Maximum Ratings(Note 1) Voltage at Any Pin Operating Temperature Range Storage Temperature Range Operating VCC Range Maximum VCC Voltage Power Dissipation (PD) Dual-In-Line Small Outline 700 mW 500 mW −0.3V to VCC + 0.3V −40°C to +85°C −65°C to +150°C 3.0V to 15V 18V Lead Temperature (Soldering, 10 seconds) 300°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. DC Electrical Characteristics Min/Max limits apply across the guaranteed temperature range unless otherwise noted Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC VIN(1) VIN(0) VOUT(1) VOUT(0) VIN(1) VIN(0) VOUT(1) VOUT(0) Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage Logical “1” Input Current Logical “0” Input Current Supply Current Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5.0V, IO = −10 µA VCC = 10V, IO = −10 µA VCC = 5.0V, IO = 10 µA VCC = 10V, IO = 10 µA VCC = 15V, VIN = 15V VCC = 15V, VIN = 0V VCC = 15V 74C, VCC = 4.75V 74C, VCC = 4.75V 74C, VCC = 4.75V, IO = −10 µA 74C, VCC = 4.75V, IO = 10 µA 74C, VCC = 4.75V 74C, VCC = 4.75V 74C, VCC = 4.75V, IO = −360 µA 74C, VCC = 4.75V, IO = 360 µA 2.4 0.4 4.0 1.0 4.4 0.4 VCC − 1.5 0.8 −1.0 0.005 −0.005 0.01 15 4.5 9.0 0.5 1.0 1.0 3.5 8.0 1.5 2.0 V V V V V V V V µA µA µA V V V V V V V V Parameter Conditions Min Typ Max Units LOW POWER TO CMOS CMOS TO LOW POWER OUTPUT DRIVE (see Family Characteristics Data Sheet) TA = 25°C (short circuit current) ISOURCE ISOURCE ISINK ISINK Output Source Current Output Source Current Output Sink Current Output Sink Current VCC = 5.0V, VIN(0) = 0V, VOUT = 0V VCC = 10V, VIN(0) = 0V, VOUT = 0V VCC = 5.0V, VIN(1) = 5.0V, VOUT = VCC VCC = 10V, VIN(1) = 10V, VOUT = VCC −1.75 −8.0 1.75 8.0 mA mA mA mA AC Electrical Characteristics TA = 25°C, CL = 50 pF, unless otherwise specified Symbol Parameter MM74C00, MM74C02, MM74C04 tpd0, tpd1 CIN CPD Propagation Delay Time to Logical “1” or “0” Input Capacitance Power Dissipation Capacitance (Note 2) Conditions VCC = 5.0V VCC = 10V (Note 3) Per Gate or Inverter (Note 4) Min Typ Max Units 50 30 6.0 12 90 60 ns ns pF pF Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note— AN-90. www.fairchildsemi.com 2 MM74C00 • MM74C02 • MM74C04 Typical Performance Characteristics Gate Transfer Characteristics Propagation Delay vs Ambient Temperature MM74C00, MM74C02, MM74C04 Guaranteed Noise Margin Over Temperature vs VCC Propagation Delay vs Ambient Temperature MM74C00, MM74C02, MM74C04 Power Dissipation vs Frequency MM74C00, MM74C02, MM74C04 Propagation Delay Time vs Load Capacitance MM74C00, MM74C02, MM74C04 3 www.fairchildsemi.com MM74C00 • MM74C02 • MM74C04 Switching Time Waveforms and AC Test Circuit CMOS to CMOS Delays measured with input tr, tf ≤ 20 ns. www.fairchildsemi.com 4 MM74C00 • MM74C02 • MM74C04 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A 5 www.fairchildsemi.com MM74C00 • MM74C02 • MM74C04 Quad 2-Input NAND Gate • Quad 2-Input NOR Gate • Hex Inverter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.