MM74C174N

MM74C174 Hex D-Type Flip-Flop October 1987 Revised January 1999 MM74C174 Hex D-Type Flip-Flop General Description The MM74C174 hex D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors. All have a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clear is independent of clock and accomplished by a low level at the clear input. All inputs are protected by diodes to VCC and GND. Features s Wide supply voltage range: s Guaranteed noise margin: s High noise immunity: 3.0V to 15V 1.0V 0.45 VCC (typ.) s Low power TTL compatibility: Fan out of 2 driving 74L Ordering Code: Order Number MM74C174M MM74C174N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Truth Table Inputs Clear L H H H Clock X ↑ ↑ L D X H L X Output Q L H L Q Top View © 1999 Fairchild Semiconductor Corporation DS005899.prf www.fairchildsemi.com MM74C174 Logic Diagrams www.fairchildsemi.com 2 MM74C174 Absolute Maximum Ratings(Note 1) Voltage at Any Pin Operating Temperature Range Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range 700 mW 500 mW 3.0V to 15V −0.3V to VCC +0.3V −40°C to +85°C −65°C to +150°C Absolute Maximum VCC Lead Temperature (Soldering, 10 seconds) 18V 260°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation. DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC VIN(1) VIN(0) VOUT(1) VOUT(0) ISOURCE ISOURCE ISINK ISINK Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage Logical “1” Input Current Logical “0” Input Current Supply Current Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage Output Source Current (P-Channel) Output Source Current (P-Channel) Output Sink Current (N-Channel) Output Sink Current (N-Channel) VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V, IO = −10 µA VCC = 10V, IO = −10 µA VCC = 5V, IO = 10 µA VCC = 10V, IO = 10 µA VCC = 15V, VIN = 15V VCC = 15V, VIN = 0V VCC = 15V VCC = 4.75V VCC = 4.75V VCC = 4.75V, IO = −360 µA VCC = 4.75V, IO = 360 µA VCC = 5V TA = 25°C, VOUT = 0V VCC = 10V TA = 25°C, VOUT = 0V VCC = 5V TA = 25°C, VOUT = 0V VCC = 5V TA = 25°C, VOUT = 0V 8.0 16 mA 1.75 3.6 mA −8.0 −15 mA −1.75 −3.3 2.4 0.4 VCC−1.5 0.8 −1.0 0.005 −0.005 0.05 300 4.5 9.0 0.5 1.0 1.0 3.5 8.0 1.5 2.0 V V V V V V V V µA µA µA V V V V mA Parameter Conditions Min Typ Max Units CMOS/LPTTL INTERFACE OUTPUT DRIVE (See Family Characteristics Data Sheet) (short circuit current) 3 www.fairchildsemi.com MM74C174 AC Electrical Characteristics TA = 25°C, CL = 50 pF, unless otherwise noted Symbol tpd tpd tS1, tS0 tH1, tH0 tW tW tr, tf fMAX CIN CPD Parameter Propagation Delay Time to a Logical “0” or Logical “1” from Clock to Q Propagation Delay Time to a Logical “0” from Clear Time Prior to Clock Pulse that Data Must be Present Time after Clock Pulse that Data Must be Held Minimum Clock Pulse Width Minimum Clear Pulse Width Maximum Clock Rise and Fall Time Maximum Clock Frequency Input Capacitance Power Dissipation Capacitance (Note 2) Conditions Min Typ 150 70 110 50 75 25 0 0 −10 −5.0 50 35 65 35 15 5.0 2.0 5.0 >1200 >1200 6.5 12 11 5.0 95 250 100 140 70 Max 300 110 300 110 Units ns ns ns ns ns ns ns ns ns ns ns ns µs µs MHz MHz pF pF pF VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V Clear Input (Note 3) Any Other Input Per Package (Note 4) Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note AN-90. AC Test Circuit Switching Time Waveforms CMOS to CMOS tr = tf = 20 ns www.fairchildsemi.com 4 MM74C174 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 5 www.fairchildsemi.com MM74C174 Hex D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.