MM74C74N

MM74C74 Dual D-Type Flip-Flop October 1987 Revised May 2002 MM74C74 Dual D-Type Flip-Flop General Description The MM74C74 dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors. Each flip-flop has independent data, preset, clear and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset or clear is independent of the clock and accomplished by a low level at the preset or clear input. Features s Supply voltage range: 3V to 15V Drive 2 LPT2L loads s Tenth power TTL compatible: s Low power: 50 nW (typ.) s High noise immunity: 0.45 VCC (typ.) s Medium speed operation: 10 MHz (typ.) with 10V supply Applications • Automotive • Data terminals • Instrumentation • Medical electronics • Alarm system • Industrial electronics • Remote metering • Computers Ordering Code: Order Number MM74C74M MM74C74N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Preset 0 0 1 1 Clear 0 1 0 1 Qn 0 1 0 Qn (Note 1) Qn 0 0 1 Qn (Note 1) Note 1: No change in output from previous state. Note: A logic “0” on clear sets Q to logic “0”. A logic “0” on preset sets Q to logic “1”. Top View © 2002 Fairchild Semiconductor Corporation DS005885 www.fairchildsemi.com MM74C74 Logic Diagram www.fairchildsemi.com 2 MM74C74 Absolute Maximum Ratings(Note 2) Voltage at Any Pin (Note 2) Operating Temperature Range Storage Temperature Range Power Dissipation Dual-In-Line Small Outline Lead Temperature (Soldering, 10 seconds) Operating VCC Range VCC (Max) 260°C 3V to 15V 18V 700 mW 500 mW Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. −0.3V to VCC +0.3V −55°C to +125°C −65°C to +150°C DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC VIN(1) VIN(0) VOUT(1) VOUT(0) ISOURCE ISOURCE ISINK ISINK Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage Logical “1” Input Current Logical “0” Input Current Supply Current Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage Output Source Current Output Source Current Output Sink Current Output Sink Current VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 15V VCC = 15V VCC = 15V VCC = 4.75V VCC = 4.75V VCC = 4.75V, ID = −360 µA VCC = 4.75V, ID = 360 µA VCC = 5V, VIN(0) = 0V TA = 25°C, VOUT = 0V VCC = 10V, VIN(0) = 0V TA = 25°C, VOUT = 0V VCC = 5V, VIN(1) = 5V TA = 25°C, VOUT = V CC VCC = 10V, VIN(1) = 10V TA = 25°C, VOUT = V CC 2.4 0.4 VCC− 1.5 0.8 V V V −1.0 0.05 60 4.5 9.0 0.5 1.0 1.0 3.5 80 1.5 2.0 V V V V µA µA µA Min Typ Max Units CMOS/LPTTL INTERFACE OUTPUT DRIVE (See Family Characteristics Data Sheet) −1.75 −8.0 1.75 8.0 mA mA mA mA 3 www.fairchildsemi.com MM74C74 AC Electrical Characteristics TA = 25°C, CL = 50 pF, unless otherwise noted Symbol CIN tpd Parameter Input Capacitance Propagation Delay Time to a Logical “0” tpd0 or Logical “1” tpd1 from Clock to Q or Q tpd tpd tS0, tS1 tH0, tH1 tPW1 tPW2 tr, tf fMAX CPD Propagation Delay Time to a Logical “0” from Preset or Clear Propagation Delay Time to a Logical “1” from Preset or Clear Time Prior to Clock Pulse that Data Must be Present tSETUP Time after Clock Pulse that Data Must be Held Minimum Clock Pulse Width (tWL = tWH) Minimum Preset and Clear Pulse Width Maximum Clock Rise and Fall Time Maximum Clock Frequency Power Dissipation Capacitance (Note 3) Conditions Any Input (Note 4) VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V (Note 5) 15.0 5.0 2.0 5.0 3.5 8.0 40 100 40 Min Typ 5.0 180 70 180 70 250 100 50 20 −20 −8.0 100 40 100 40 0 0 250 100 160 70 300 110 300 110 400 150 Max Units pF ns ns ns ns ns ns ns µs MHz pF Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: Capacitance is guaranteed by periodic testing. Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note— AN-90. Typical Applications Ripple Counter (Divide by 2n) 74C Compatibility Shift Register Guaranteed Noise Margin as a Function of VCC www.fairchildsemi.com 4 MM74C74 Switching Time Waveform CMOS to CMOS tr = tf = 20 ns AC Test Circuit 5 www.fairchildsemi.com MM74C74 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 6 MM74C74 Dual D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com