MM74HC123AN

MM74HC123A Dual Retriggerable Monostable Multivibrator September 1983 Revised February 1999 MM74HC123A Dual Retriggerable Monostable Multivibrator General Description The MM74HC123A high speed monostable multivibrators (one shots) utilize advanced silicon-gate CMOS technology. They feature speeds comparable to low power Schottky TTL circuitry while retaining the low power and high noise immunity characteristic of CMOS circuits. Each multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be used as an inhibit input. Also included is a clear input that when taken low resets the one shot. The MM74HC123A can be triggered on the positive transition of the clear while A is held LOW and B is held HIGH. The MM74HC123A is retriggerable. That is it may be triggered repeatedly while their outputs are generating a pulse and the pulse will be extended. Pulse width stability over a wide range of temperature and supply is achieved using linear CMOS techniques. The output pulse equation is simply: PW = (REXT) (CEXT); where PW is in seconds, R is in ohms, and C is in farads. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features s Typical propagation delay: 25 ns s Wide power supply range: 2V–6V s Low quiescent current: 80 µA maximum (74HC Series) s Low input current: 1 µA maximum s Fanout of 10 LS-TTL loads s Simple pulse width formula T = RC s Wide pulse range: 400 ns to ∞ (typ) s Part to part variation: ±5% (typ) s Schmitt Trigger A & B inputs enable infinite signal input rise and fall times. Ordering Code: Order Number MM74HC123AM MM74HC123ASJ MM74HC123AMTC MM74HC123AN Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignment for DIP, SOIC, SOP and TSSOP Timing Component Note: Pin 6 and Pin 14 must be hard-wired to GND. Top View © 1999 Fairchild Semiconductor Corporation DS005206.prf www.fairchildsemi.com MM74HC123A Truth Table Inputs Clear L X X H H ↑ H L ↑ ↓ HIGH Level LOW Level Transition from LOW-to-HIGH Transition from HIGH-to-LOW = One HIGH Level Pulse = One LOW Level Pulse X = Irrelevant = = = = Outputs B X X L ↑ H H Q L L Q H H A X H X L ↓ L    L H  Logic Diagram www.fairchildsemi.com 2 MM74HC123A Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C 600 mW 500 mW −0.5V to +7.0V −1.5V to VCC +1.5V −0.5V to VCC +0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (Clear Input) (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns −40 +85 °C 2 0 Max 6 VCC Units V V Note 1: M aximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation Temperature Derating: Plastic “N” Package: − 12mW/°C from 65°C to 85°C DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA Conditions (Note 4) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 TA = 25°C Typ 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.5 ±0.1 8.0 36 0.33 0.7 80 1.0 2.0 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±5.0 ±1.0 80 110 1.3 2.6 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±5.0 ±1.0 160 130 1.6 3.2 Units V V V V V V V V V V 4.5V 6.0V 2.0V 4.5V 6.0V V V V V V V 4.5V 6.0V 6.0V 6.0V 6.0V 2.0V 4.5V 6.0V V V µA µA µA µA mA mA VIN = VIH or VIL |IOUT| ≤ 4.0 mA |IOUT| ≤ 5.2 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA VIN = VIH or VIL |IOUT| ≤ 4 mA |IOUT| ≤ 5.2 mA IIN IIN ICC ICC Maximum Input Current (Pins 7, 15) Maximum Input Current (all other pins) Maximum Quiescent Supply VIN = VCC or GND Current (standby) Maximum Active Supply Current (per monostable) IOUT = 0 µA VIN= VCC or GND R/CEXT = 0.5VCC VIN = VCC or GND VIN = VCC or GND Note 4: For a power supply of 5V ±10% the worst-case output voltages (VOH, VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst-case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC123A AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol tPLH tPHL tPHL tPLH tW tREM tWQ(MIN) tWQ Parameter Maximum Trigger Propagation Delay A, B or Clear to Q Maximum Trigger Propagation Delay A, B or Clear to Q Maximum Propagation Delay, Clear to Q Maximum Propagation Delay, Clear to Q Minimum Pulse Width, A, B or Clear Minimum Clear Removal Time Minimum Output Pulse Width Output Pulse Width CEXT = 28 pF REXT = 2 kΩ CEXT = 1000 pF REXT = 10 kΩ 10 µs 400 20 22 14 27 33 26 0 ns ns ns ns ns 25 42 ns Conditions Typ 22 Limit 33 Units ns AC Electrical Characteristics CL = 50 pF tr = tf = 6 ns (unless otherwise specified) Symbol tPLH Parameter Maximum Trigger Propagation Delay, A, B or Clear to Q tPHL Maximum Trigger Propagation Delay, A, B or Clear to Q tPHL Maximum Propagation Delay Clear to Q tPLH Maximum Propagation Delay Clear to Q tW Minimum Pulse Width A, B, Clear tREM Minimum Clear Removal Time tTLH, tTHL Maximum Output Rise and Fall Time tWQ(MIN) Minimum Output Pulse Width tWQ CIN CIN CPD Output Pulse Width Maximum Input Capacitance (Pins 7 & 15) Maximum Input Capacitance (other inputs) Power Dissipation Capacitance Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC V CC, and the no load dynamic current consumption, IS = CPD VCC f + I CC. Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA = 25°C Typ 77 26 21 88 29 24 54 23 19 56 25 20 57 17 12 169 42 32 197 48 38 114 34 28 116 36 29 123 30 21 0 0 0 30 8 7 1.5 450 380 1 1 12 6 0.9 1.1 20 10 75 15 13 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 194 51 39 229 60 46 132 41 33 135 42 34 144 37 27 0 0 0 95 19 16 210 57 44 250 67 51 143 45 36 147 46 37 157 42 30 0 0 0 110 22 19 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns ns CEXT = 28 pF REXT = 2 kΩ REXT = 6 kΩ (VCC = 2V) CEXT = 0.1 µF REXT = 10 kΩ Min Mx a 2.0V 4.5V 6.0V 5.0V 5.0V 0.86 1.14 20 10 0.85 1.15 20 10 ms ms pF pF pF (Note 5) 70 www.fairchildsemi.com 4 MM74HC123A Theory of Operation 1POSITIVE EDGE TRIGGER 2NEGATIVE EDGE TRIGGER 3POSITIVE EDGE TRIGGER 4POSITIVE EDGE RE-TRIGGER (PULSE LENGTHENING) 5RESET PULSE SHORTENING 6CLEAR TRIGGER FIGURE 1. TRIGGER OPERATION As shown in Figure 1 and the logic diagram, before an input trigger occurs, the one shot is in the quiescent state with the Q output LOW, and the timing capacitor CEXT completely charged to VCC. When the trigger input A goes from VCC to GND (while inputs B and clear are held to VCC) a valid trigger is recognized, which turns on comparator C1 and Nchannel transistor N11. At the same time the output latch is set. With transistor N1 on, the capacitor C EXT rapidly discharges toward GND until VREF1 is reached. At this point the output of comparator C1 changes state and transistor N1 turns off. Comparator C1 then turns off while at the same time comparator C2 turns on. With transistor N1 off, the capacitor CEXT begins to charge through the timing resistor, REXT, toward VCC. When the voltage across CEXT equals VREF2, comparator C2 changes state causing the output latch to reset (Q goes LOW) while at the same time disabling comparator C2. This ends the timing cycle with the monostable in the quiescent state, waiting for the next trigger. A valid trigger is also recognized when trigger input B goes from GND to VCC (while input A is at GND and input clear is at VCC2). The MM74HC123A can also be triggered when clear goes from GND to VCC (while A is at GND and B is at VCC6). It should be noted that in the quiescent state CEXT is fully charged to VCC causing the current through resistor REXT to be zero. Both comparators are “off” with the total device current due only to reverse junction leakages. An added feature of the MM74HC123A is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is independent of the value of CEXT, REXT, or the duty cycle of the input waveform. RETRIGGER OPERATION The MM74HC123A is retriggered if a valid trigger occurs 3 followed by another trigger 4 before the Q output has returned to the quiescent (zero) state. Any retrigger, after the timing node voltage at the R/CEXT pin has begun to rise from VREF1, but has not yet reached VREF2, will cause an increase in output pulse width T. When a valid retrigger is initiated 4, the voltage at the R/CEXT pin will again drop to VREF1 before progressing along the RC charging curve toward VCC. The Q output will remain HIGH until time T, after the last valid retrigger. Because the trigger-control circuit flip-flop resets shortly after CX has discharged to the reference voltage of the lower reference circuit, the minimum retrigger time, trr is a function of internal propagation delays and the discharge time of CX: Another removal/retrigger time occurs when a short clear pulse is used. Upon receipt of a clear, the one shot must charge the capacitor up to the upper trip point before the one shot is ready to receive the next trigger. This time is dependent on the capacitor used and is approximately: 5 www.fairchildsemi.com MM74HC123A RESET OPERATION These one shots may be reset during the generation of the output pulse. In the reset mode of operation, an input pulse on clear sets the reset latch and causes the capacitor to be fast charged to VCC by turning on transistor Q1 5. When the voltage on the capacitor reaches VREF2, the reset latch will clear and then be ready to accept another pulse. If the clear input is held low, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change. Since the Q output is reset when an input lowlevel is detected on the Clear input, the output pulse T can be made significantly shorter than the minimum pulse width specification. Typical Output Pulse Width vs. Timing Components Typical 1ms Pulse Width Variation vs. Supply Typical Distribution of Output Pulse Width, Part to Part Minimum REXT vs. Supply Voltage Typical 1ms Pulse Width Variation vs. Temperature Note: R and C are not subjected to temperature. The C is polypropylene. www.fairchildsemi.com 6 MM74HC123A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com MM74HC123A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 8 MM74HC123A Dual Retriggerable Monostable Multivibrator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.