MM74HC126M

MM74HC125/MM74HC126 3-STATE Quad Buffers September 1983 Revised January 2005 MM74HC125/MM74HC126 3-STATE Quad Buffers General Description The MM74HC125 and MM74HC126 are general purpose 3-STATE high speed non-inverting buffers utilizing advanced silicon-gate CMOS technology. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs. The MM74HC125 require the 3-STATE control input C to be taken high to put the output into the high impedance condition, whereas the MM74HC126 require the control input to be low to put the output into high impedance. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features s Typical propagation delay: 13 ns s Wide operating voltage range: 2–6V s Low input current: 1 µA maximum s Low quiescent current: 80 µA maximum (74HC) s Fanout of 15 LS-TTL loads Ordering Code: Order Number MM74HC125M MM74HC125SJ MM74HC125MTC MM74HC125MTCX-NL MM74HC125N MM74HC126M MM74HC126MX_NL MM74HC126SJ MM74HC126MTC MM74HC126MTCX_NL MM74HC126N N14A M14A M14A M14D MTC14 MTC14 N14A Package Number M14A M14D MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.) Pb-Free package per JEDEC J-STD-020B. © 2005 Fairchild Semiconductor Corporation DS005308 www.fairchildsemi.com MM74HC125/MM74HC126 Connection Diagrams Pin Assignments for DIP, SOIC, SOP and TSSOP Top View (MM74HC125) Top View (MM74HC126) Truth Tables Inputs A H L X C L L H Output Y H L Z A H L X Inputs C H H L Output Y H L Z www.fairchildsemi.com 2 MM74HC125/MM74HC126 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C (Note 4) VCC 2.0V 4.5V 6.0V VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA VIN = VIH or VIL |IOUT| ≤ 6.0 mA |IOUT| ≤ 7.8 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA VIN = VIH or VIL |IOUT| ≤ 6.0 mA |IOUT| ≤ 7.8 mA IOZ Maximum 3-STATE Output Leakage Current IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VIH or VIL VOUT = VCC or GND Cn = Disabled VIN = VCC or GND VIN = VCC or GND IOUT = 0 µA 6.0V 6.0V 4.5V 6.0V 6.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V Recommended Operating Conditions Min Max Units Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns 2 0 6 VCC V V −0.5 to +7.0V −1.5 to VCC +1.5V −0.5 to VCC +0.5V ±20 mA ±35 mA ±70 mA −65°C to +150°C 600 mW 500 mW −40 +85 °C Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage Conditions TA = 25°C Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.5 TA = −40 to 85°C TA = −40 to 125°C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±5 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±10 Units V V V V V V V V V V V V V V V V µA ±0.1 8.0 ±1.0 80 ±1.0 160 µA µA Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC125/MM74HC126 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 45 pF, tr = tf = 6 ns Symbol tPHL, tPLH tPZH tPHZ tPZL tPLZ Maximum Propagation Delay Time Maximum Output Enable Time to HIGH Level Maximum Output Disable Time from HIGH Level Maximum Output Enable Time to LOW Level Maximum Output Disable Time from LOW Level RL = 1 kΩ CL = 5 p F 13 25 ns RL = 1 kΩ CL = 5 pF RL = 1 kΩ 18 25 ns 17 25 ns RL = 1 kΩ 13 25 ns Parameter Conditions Typ 13 Guaranteed Limit 18 Units ns AC Electrical Characteristics VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC 2.0V 4.5V 6.0V tPLH, tPHL Maximum Propagation Delay Time tPZH, tPZL Maximum Output Enable Time tPHZ, tPLZ Maximum Output Disable Time tPZL, tPZH Maximum Output Enable Time tTLH, tTHL Maximum Output Rise and Fall Time CIN COUT CPD Input Capacitance Output Capacitance Outputs Power Dissipation Capacitance (Note 5) (per gate) Enabled Disabled 45 6 pF pF CL = 150 pF RL = 1 kΩ CL = 50 pF RL = 1 kΩ RL = 1 kΩ CL = 150 pF 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA = 25°C Typ 40 14 12 35 14 12 25 14 12 25 14 12 35 15 13 30 7 6 5 15 100 20 17 130 26 22 125 25 21 125 25 21 140 28 24 60 12 10 10 20 TA = −40 to 85°C TA = −40 to 125°C Guaranteed Limits 125 25 21 163 33 28 156 31 26 156 31 26 175 35 30 75 15 13 10 20 150 30 25 195 39 39 188 38 31 188 38 31 210 42 36 90 18 15 10 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF tPHL, tPLH Maximum Propagation Delay Time Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD V CC f + ICC. www.fairchildsemi.com 4 MM74HC125/MM74HC126 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrowy Package Number M14A 5 www.fairchildsemi.com MM74HC125/MM74HC126 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 MM74HC125/MM74HC126 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 7 www.fairchildsemi.com MM74HC125/MM74HC126 3-STATE Quad Buffers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com