MM74HC132 Quad 2-Input NAND Schmitt Trigger
September 1983 Revised January 2005
MM74HC132 Quad 2-Input NAND Schmitt Trigger
General Description
The MM74HC132 utilizes advanced silicon-gate CMOS technology to achieve the low power dissipation and high noise immunity of standard CMOS, as well as the capability to drive 10 LS-TTL loads. The 74HC logic family is functionally and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
s Typical propagation delay: 12 ns s Wide power supply range: 2V–6V s Low quiescent current: 20 µA maximum (74HC Series) s Low input current: 1 µA maximum s Fanout of 10 LS-TTL loads s Typical hysteresis voltage: 0.9V at VCC=4.5V
Ordering Code:
Order Number MM74HC132M MM74HC132MX_NL MM74HC132SJ MM74HC132MTC MM74HC132N Package Number M14A M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.) Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Assignment for DIP, SOIC, SOP, and TSSOP
Logic Diagram
Top View
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DS005309
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MM74HC132
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C (Note 4) 600 mW 500 mW
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) 2 0 Max 6 VCC Units V V
−0.5 to +7.0V −1.5 to VCC +1.5V −0.5 to VCC +0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C
−40
+125
°C
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol VT+ Parameter Positive Going Threshold Voltage
Conditions Min
VCC 2.0V 4.5V 6.0V
T A = 2 5 °C Typ 1.0 2.0 3.0 1.5 3.15 4.2 0.3 0.9 1.2 1.0 2.2 3.0 0.2 0.4 0.5 1.0 1.4 1.5 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 2.0
TA = -40 to 85°C TA = -40 to 125°C Guaranteed Limits 1.0 2.0 3.0 1.5 3.15 4.2 0.3 0.9 1.2 1.0 2.2 3.0 0.2 0.4 0.5 1.0 1.4 1.5 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 20 1.0 2.0 3.0 1.5 3.15 4.2 0.3 0.9 1.2 1.0 2.2 3.0 0.2 0.4 0.5 1.0 1.4 1.5 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 40
Units V V V V V V V V V V V V V V V V V V V V V V V V V V V V µA µA
Max
2.0V 4.5V 6.0V
VT−
Negative Going Threshold Voltage
Min
2.0V 4.5V 6.0V
Max
2.0V 4.5V 6.0V
VH
Hysteresis Voltage
Min
2.0V 4.5V 6.0V
Max
2.0V 4.5V 6.0V
VOH
Minimum HIGH Level Output Voltage
VIN = VIH or VIL |IOUT| ≤ 20 µA VIN = VIH or VIL |IOUT| ≤ 4.0 mA |IOUT| ≤ 5.2 mA
2.0V 4.5V 6.0V 4.5V 6.0V 2.0V 4.5V 6.0V 4.5V 6.0V 6.0V 6.0V
VOL
Maximum LOW Level Output Voltage
VIN = VIH or VIL |IOUT| ≤ 20 µA VIN = VIH or VIL |IOUT| ≤ 4.0 mA |IOUT| ≤ 5.2 mA
IIN ICC
Maximum Input Current Maximum Quiescent Supply Current
VIN = VCC or GND VIN = VCC or GND IOUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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MM74HC132
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol tPHL, tPLH Parameter Maximum Propagation Delay Conditions Typ 12 Guaranteed Limit 20 Units ns
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol tPHL, tPLH Maximum Propagation Delay tTLH, tTHL Maximum Output Rise and Fall Time CPD CIN Power Dissipation Capacitance (Note 5) Maximum Input Capacitance 5 10 10 pF
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC.
Parameter
Conditions
VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V
TA = 25°C Typ 63 13 11 30 8 7 130 125 25 21 75 15 13
TA= −40 to 85°C TA= −55 to 125°C Guaranteed Limits 158 32 27 95 19 16 186 37 32 110 22 19
Units ns ns ns ns ns ns pF
(per gate)
3
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MM74HC132
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
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MM74HC132
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
5
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MM74HC132
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
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6
MM74HC132 Quad 2-Input NAND Schmitt Trigger
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
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