MM74HC164

MM74HC164 8-Bit Serial-in/Parallel-out Shift Register September 1983 Revised January 2005 MM74HC164 8-Bit Serial-in/Parallel-out Shift Register General Description The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low consumption of standard CMOS integrated circuits. It also offers speeds comparable to low power Schottky devices. This 8-bit shift register has gated serial inputs and CLEAR. Each register bit is a D-type master/slave flip-flop. Inputs A & B permit complete control over the incoming data. A LOW at either or both inputs inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A high level on one input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at the CLEAR input. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features s Typical operating frequency: 50 MHz s Typical propagation delay: 19 ns (clock to Q) s Wide operating supply voltage range: 2V to 6V s Low input current: 1 µA maximum s Low quiescent supply current: 80 µA maximum (74HC Series) s Fanout of 10 LS-TTL loads Ordering Code: Order Number MM74HC164M MM74HC164MX_NL MM74HC164MTC MM74HC164MTCX_NL MM74HC164N Package Number M14A M14A MTC14 MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. © 2005 Fairchild Semiconductor Corporation DS005315 www.fairchildsemi.com MM74HC164 Connection Diagram Truth Table Inputs Clear Clock L H H H H X L A X X H L X Top View Outputs B X X H X L QA L QAO H L L QB L QBO QAn QAn QAn ... QH L QHO QGn QGn QGn ↑ ↑ ↑ H = H IGH Level (steady state), L = LOW Level (steady state) X = Irrelevant (any input, including transitions) ↑ = Transition from LOW-to-HIGH level. QAO, QBO, QHO = the level of QA, QB, or QH, respectively, before the indicated steady state input conditions were established. QAn, QGn = The level of QA or QG before the most recent ↑ transition of the clock; indicated a one-bit shift. Logic Diagram www.fairchildsemi.com 2 MM74HC164 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C 600 mW 500 mW Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns 0 VCC V 2 Max 6 Units V −0.5 to +7.0V −1.5 to VCC +1.5V −0.5 to VCC +0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C −40 +85 °C Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA Conditions (Note 4) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 T A = 2 5 °C Typ 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 8.0 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 80 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 160 µA µA V V V V Units VIN = VIH or VIL |IOUT| ≤ 4.0 mA |IOUT| ≤ 5.2 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| ≤ 4.0 mA |IOUT| ≤ 5.2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VCC or GND IOUT = 0 µA 6.0V VIN = VCC or GND 4.5V 6.0V 6.0V 4.5V 6.0V Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC164 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol fMAX tPHL, tPLH tPHL tREM tS tH tW Parameter Maximum Operating Frequency Maximum Propagation Delay Clock to Output Maximum Propagation Delay Clear to Output Minimum Removal Time, Clear to Clock Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data Minimum Pulse Width Clear or Clock 10 16 ns 1 5 ns 12 20 ns −2 0 ns 23 35 ns 19 Conditions Typ Guaranteed Limit 30 30 Units MHz ns AC Electrical Characteristics CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Operating Frequency Conditions VCC 2.0V 4.5V 6.0V tPHL, tPLH Maximum Propagation Delay Clock to Output tPHL Maximum Propagation Delay Clear to Output tREM Minimum Removal Time Clear to Clock tS Minimum Setup Time Data to Clock tH Minimum Hold Time Clock to Data tW Minimum Pulse Width Clear or Clock tTHL, tTLH Maximum Output Rise and Fall Time tr, tf Maximum Input Rise and Fall Time CPD CIN Power Dissipation Capacitance (Note 5) Maximum Input Capacitance (per package) 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 5.0V 150 5 10 10 10 115 13 20 140 28 24 −7 −3 −2 25 14 12 −2 0 1 22 11 10 T A = 2 5 °C Typ 5 27 31 175 35 30 205 41 35 0 0 0 100 20 17 5 5 5 80 16 14 75 15 13 1000 500 400 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 4 21 24 218 44 38 256 51 44 0 0 0 125 25 21 5 5 5 100 20 18 95 19 16 1000 500 400 3 18 20 254 51 44 297 59 51 0 0 0 150 30 25 5 5 5 120 24 20 110 22 19 1000 500 400 pF pF ns ns ns ns ns ns ns ns MHz Units Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. www.fairchildsemi.com 4 MM74HC164 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com MM74HC164 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 6 MM74HC164 8-Bit Serial-in/Parallel-out Shift Register Physical Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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