MM74HC240_05

MM74HC240 Inverting Octal 3-STATE Buffer September 1983 Revised May 2005 MM74HC240 Inverting Octal 3-STATE Buffer General Description The MM74HC240 3-STATE buffer utilizes advanced silicon-gate CMOS technology. It possesses high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the advantage of CMOS circuitry, i.e., high noise immunity and low power consumption. It has a fanout of 15 LS-TTL equivalent inputs. The MM74HC240 is an inverting buffer and has two active LOW enables (1G and 2G). Each enable independently controls 4 buffers. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features s Typical propagation delay: 12 ns s 3-STATE outputs for connection to system buses s Wide power supply range: 2–6V s Low quiescent supply current: 80 PA (74 Series) s Output current: 6 mA Ordering Code: Order Number MM74HC240WM MM74HC240SJ MM74HC240MTC MM74HC240N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table 1G L L H H H HIGH Level L LOW Level Z HIGH Impedance 1A L H L H 1Y H L Z Z 2G L L H H 2A L H L H 2Y H L Z Z Top View © 2005 Fairchild Semiconductor Corporation DS005020 www.fairchildsemi.com MM74HC240 Logic Diagram www.fairchildsemi.com 2 MM74HC240 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC VCC 4.5V 6.0V VCC 2.0V 1000 500 400 ns ns ns 2 0 Max 6 VCC Units V V 0.5 to 7.0V 1.5 to VCC 1.5V DC Output Voltage (VOUT) 0.5 to VCC 0.5V Clamp Diode Current (IIK, IOK) r20 mA r35 mA DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) r70 mA Storage Temperature Range (TSTG) 65qC to 150qC DC Input Voltage (VIN) (Note 3) S.O. Package only 600 mW 500 mW 260qC 40 85 qC Power Dissipation (PD) Lead Temperature (TL) (Soldering 10 seconds) Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package:  12 mW/qC from 65qC to 85qC. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VI N VIH or VIL Conditions (Note 4) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 2 5 qC TA 40 to 85qC TA 55 to 125qC Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 Units V V V V V V V V V V V V V V V V |IOUT| d 20 PA 2.0V 4.5V 6.0V VIN VIH or VIL 4.5V 6.0V 2.0V 4.5V 6.0V |IOUT| d 6.0 mA |IOUT| d 7.8 mA VOL Maximum LOW Level Output Voltage VIN VIH or VIL |IOUT| d 20 PA VIN VIH or VIL 4.5V 6.0V 6.0V 6.0V |IOUT| d 6.0 mA |IOUT| d 7.8 mA IIN IOZ Maximum Input Current Maximum 3-STATE Output Leakage Current ICC Maximum Quiescent Supply Current VIN VIN VOUT G VIN IOUT VCC or GND VIH or VIL VCC or GND VIL VCC or GND 0 PA r0.1 r0.5 r1.0 r5 r1.0 r10 PA PA VIH, G 6.0V 8.0 80 160 PA Note 4: For a power supply of 5V r10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC240 AC Electrical Characteristics VCC 5V, TA 25qC, tr tf 6 ns Conditions CL RL CL RL CL 45 pF 1 k: 45 pF 1 k: 5 pF Typ 12 14 13 Guaranteed Limit 18 28 25 Units ns ns ns Symbol tPHL, tPLH tPZH, tPZL tPHZ, tPLZ Parameter Maximum Propagation Delay Maximum Enable Delay to Active Output Maximum Disable Delay from Active Output AC Electrical Characteristics VCC 2.0V to 6.0V, CL 50 pF, tr tf 6 ns (unless otherwise specified) Conditions CL CL CL CL CL CL tPZH, tPZL Maximum Output Enable TIme RL CL CL CL CL CL CL tPHZ, tPLZ Maximum Output Disable Time tTLH, tTHL Maximum Output Rise and Fall Time CPD Power Dissipation Capacitance (Note 5) CIN COUT Maximum Input Capacitance Maximum Output Capacitance (per buffer) G G VIH VIL 12 50 5 10 10 20 10 20 10 20 pF pF pF pF RL CL 50 pF 150 pF 50 pF 150 pF 50 pF 150 pF 1 k: 50 pF 150 pF 50 pF 150 pF 50 pF 150 pF 1 k: 50 pF 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 75 100 15 20 13 17 75 15 13 150 200 30 40 26 34 150 30 26 60 12 10 189 252 38 50 32 43 189 38 32 75 15 13 224 298 45 60 38 51 224 45 38 90 18 15 ns ns ns ns ns ns ns ns ns ns ns ns VCC 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V TA Typ 55 80 12 22 11 28 100 150 20 30 17 26 2 5 qC TA Symbol Parameter 40 to 85qC TA 55 to 125qC Guaranteed Limits 126 190 25 38 21 32 149 224 30 45 25 38 Units ns ns ns ns ns ns tPHL, tPLH Maximum Propagation Delay Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC f  I CC. CPD VCC2 f  ICC VCC, and the no load dynamic current consumption, www.fairchildsemi.com 4 MM74HC240 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com MM74HC240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 MM74HC240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com MM74HC240 Inverting Octal 3-STATE Buffer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com