MM74HC244SJ

MM74HC244 Octal 3-STATE Buffer September 1983 Revised May 2005 MM74HC244 Octal 3-STATE Buffer General Description The MM74HC244 is a non-inverting buffer and has two active low enables (1G and 2G); each enable independently controls 4 buffers. This device does not have Schmitt trigger inputs. These 3-STATE buffers utilize advanced silicon-gate CMOS technology and are general purpose high speed non-inverting buffers. They possess high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the advantage of CMOS circuitry, i.e., high noise immunity, and low power consumption. All three devices have a fanout of 15 LS-TTL equivalent inputs. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features s Typical propagation delay: 14 ns s 3-STATE outputs for connection to system buses s Wide power supply range: 2–6V s Low quiescent supply current: 80 PA s Output current: 6 mA Ordering Code: Order Number MM74HC244WM MM74HC244SJ MM74HC244MTC MM74HC244N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table 1G L L H H H HIGH Level L LOW Level Z High Impedance 1A L H L H 1Y L H Z Z 2G L L H H 2A L H L H 2Y L H Z Z Top View © 2005 Fairchild Semiconductor Corporation DS005327 www.fairchildsemi.com MM74HC244 Logic Diagram www.fairchildsemi.com 2 MM74HC244 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260qC 600 mW 500 mW Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC VCC VCC 2.0V 4.5V 6.0V 1000 500 400 ns ns ns 0 VCC V 2 Max 6 Units V 0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r 20 mA r 35 mA r 70 mA 65qC to 150qC 40 85 qC Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package:  12 mW/qC from 65qC to 85qC. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN VIH or VIL (Note 4) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 1.9 4.4 5.9 3.98 5.4 0.1 0.1 0.1 0.26 0.26 2 5 qC TA Conditions 40 to 85qC TA Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 55 to 125qC 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 Units V V V V V V V V V V V V V V V V V |IOUT | d 20 PA 2.0V 4.5V 6.0V VIN VIH or VIL 4.5V 6.0V 2.0V 4.5V 6.0V |IOUT | d 6.0 mA |IOUT | d 7.8 mA VOL Maximum LOW Level Output Voltage VIN VIH or VIL |IOUT | d 20 PA VIN VIH or VIL 4.5V 6.0V 6.0V 6.0V |IOUT | d 6.0 mA |IOUT | d 7.8 mA IIN IOZ Maximum Input Current Maximum 3-STATE Output Leakage Current ICC Maximum Quiescent Supply Current VIN VOUT G VIN IOUT VIH VCC or GND 0 PA VIH, or VIL VCC or GND VIN VCC or GND r 0.1 r 0.5 r 1.0 r5 r1.0 r10 PA PA 6.0V 8.0 80 160 PA Note 4: For a power supply of 5V r 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC244 AC Electrical Characteristics VCC 5V, TA 25qC, tr tf 6 ns Parameter Conditions CL RL CL RL CL 45 pF 1 k: 45 pF 1 k: 5 pF 15 25 ns Typ 14 17 Guaranteed Limit 20 28 Units ns ns Symbol tPHL, tPLH tPZH, tPZL tPHZ, tPLZ Maximum Propagation Delay Maximum Enable Delay to Active Output Maximum Disable Delay from Active Output AC Electrical Characteristics VCC 2.0V-6.0V, CL 50 pF, tr tf 6 ns (unless otherwise specified) Conditions CL CL CL CL CL CL 50 pF 150 pF 50 pF 150 pF 50 pF 150 pF 1 k: 50 pF 150 pF 50 pF 150 pF 50 pF 150 pF 1 k: 50 pF 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V (per buffer) G G VIH VIL 12 50 5 10 10 20 10 20 10 20 pF pF pF pF 75 100 15 30 13 17 75 15 13 150 200 30 40 26 34 150 30 26 60 12 10 189 252 38 50 32 43 189 38 32 75 15 13 224 298 45 60 38 51 224 45 38 90 18 15 ns ns ns ns ns ns ns ns ns ns ns ns VCC 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V TA Typ 58 83 14 17 10 14 115 165 23 33 20 28 2 5 qC TA Symbol Parameter 40 to 85qC TA Guaranteed Limits 145 208 29 42 25 35 55 to 125qC 171 246 34 49 29 42 Units ns ns ns ns ns ns tPHL, tPLH Maximum Propagation Delay tPZH, tPZL Maximum Output Enable Time RL CL CL CL CL CL CL tPHZ, tPLZ Maximum Output Disable Time tTLH, tTHL Maximum Output Rise and Fall Time CPD Power Dissipation Capacitance (Note 5) CIN COUT Maximum Input Capacitance Maximum Output Capacitance RL CL Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC f  ICC. CPD VCC2f  ICC VCC, and the no load dynamic current consumption, www.fairchildsemi.com 4 MM74HC244 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com MM74HC244 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 MM74HC244 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com MM74HC244 Octal 3-STATE Buffer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com