MM74HC259M

MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder September 1983 Revised February 1999 MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder General Description The MM74HC259 device utilizes advanced silicon-gate CMOS technology to implement an 8-bit addressable latch, designed for general purpose storage applications in digital systems. The MM74HC259 has a single data input (D), 8 latch outputs (Q1–Q8), 3 address inputs (A, B, and C), a common enable input (G), and a common CLEAR input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to be entered is held on the A, B, and C inputs. When ENABLE is taken LOW the data flows through to the addressed output. The data is stored when ENABLE transitions from LOW-to-HIGH. All unaddressed latches will remain unaffected. With enable in the HIGH state the device is deselected, and all latches remain in their previous state, unaffected by changes on the data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the enable should be held HIGH (inactive) while the address lines are changing. If enable is held HIGH and CLEAR is taken LOW all eight latches are cleared to a LOW state. If enable is LOW all latches except the addressed latch will be cleared. The addressed latch will instead follow the D input, effectively implementing a 3-to-8 line decoder. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features s Typical propagation delay: 18 ns s Wide supply range: 2–6V s Low input current: 1 µA maximum s Low quiescent current: 80 µA maximum (74HC Series) Ordering Code: Order Number MM74HC259M MM74HC259SJ MM74HC259MTC MM74HC259N Package Number Package Description M16A M16D MTC16 N16E 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Latch Selection Table Select Inputs C L L L L H H H H B L L H H L L H H A L H L H L H L H Latch Addressed 0 1 2 3 4 5 6 7 Top View H = HIGH level, L = LOW level D = the level at the data input Qi0 the level of Qi (i = 0, 1 .. .7, as appropriate) before the indicated steady-state input conditions were established. © 1999 Fairchild Semiconductor Corporation DS005006.prf www.fairchildsemi.com MM74HC259 Truth Table Inputs Outputs of Addressed Clear H H L L G L H L H Latch D Qi0 D L Each Other Output Qi0 Qi0 L L Addressable Latch Memory 8-Line Decoder Clear Function Logic Diagram www.fairchildsemi.com 2 MM74HC259 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C 600 mW 500 mW −0.5 to +7.0V −1.5 to VCC+1.5V −0.5 to VCC+0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns −40 +85 °C 2 0 Max 6 VCC Units V V Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA Conditions (Note 4) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 T A = 2 5 °C Typ 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 8.0 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 80 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 160 Units V V V V V V V V V V V V V V V V µA µA VIN = VIH or VIL |IOUT| ≤ 4.0 mA |IOUT| ≤ 5.2 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| ≤ 4.0 mA |IOUT| ≤ 5.2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VCC or GND IOUT = 0 µA 6.0V VIN = VCC or GND 4.5V 6.0V 6.0V 4.5V 6.0V Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC259 AC Electrical Characteristics (VCC = 5.0V, TA = 25°C, tr = tf = 6 ns, CL = 15 pF unless otherwise specified.) Symbol tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL tW tW tr, tf ts tH Parameter Maximum Propagation Delay Data to Output Maximum Propagation Delay Select to Output Maximum Propagation Delay Enable to Output Maximum Propagation Delay Clear to Output Minimum Enable Pulse Width Minimum Clear Pulse Width Maximum Input Rise and Fall Time Minimum Setup Time Select or Data to Enable Minimum Hold Time Data or Address to Enable −2 0 ns 15 10 10 16 16 500 20 ns ns ns ns 17 27 ns 20 35 ns 20 38 ns Conditions Typ 18 Guaranteed Limit 32 Units ns AC Electrical Characteristics tr = tf = 6 ns, CL = 50 pF, VCC = 2.0V – 6.0V Symbol Parameter Conditions VCC 2.0V 4.5V 6.0V tPHL, tPLH Maximum Propagation Delay Select to Output tPHL, tPLH Maximum Propagation Delay Enable to Output tPHL Maximum Propagation Delay Clear to Output tW Minimum Pulse Width Clear or Enable ts Minimum Setup Time Address or Data to Enable tH Minimum Hold Time Address or Data to Enable tTLH, tTHL Maximum Output Rise and Fall Time CIN CPD Input Capacitance Power Dissipation Capacitance (Note 5) Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPDs V CCsf + ICC. TA = 25°C Typ 60 19 17 72 21 18 65 27 23 50 18 16 180 37 32 220 43 37 200 40 35 150 31 26 80 16 14 100 20 15 −10 −2 −2 30 8 7 5 80 0 0 0 75 15 13 10 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 225 46 40 275 54 46 250 50 44 190 39 32 100 20 18 125 25 19 0 0 0 95 19 16 10 250 52 45 310 60 52 280 58 50 210 44 37 120 24 20 150 28 25 0 0 0 110 22 19 10 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF tPHL, tPLH Maximum Propagation Delay Data to Output 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V (per package) www.fairchildsemi.com 4 MM74HC259 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com MM74HC259 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 6 MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.