MM74HC32MX_NL

MM74HC32 Quad 2-Input OR Gate September 1983 Revised January 2005 MM74HC32 Quad 2-Input OR Gate General Description The MM74HC32 OR gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs providing high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features s Typical propagation delay: 10 ns s Wide power supply range: 2–6V s Low quiescent current: 20 µA maximum (74HC Series) s Low input current: 1 µA maximum s Fanout of 10 LS-TTL loads Ordering Code: Order Number MM74HC32M MM74HC32MX_NL MM74HC32SJ MM74HC32MTC MM74HC32MTCX_NL MM74HC32N MM74HC32N_NL Package Number M14A M14A M14D MTC14 MTC14 N14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Logic Diagram Y=A+B (1 of 4) Top View © 2005 Fairchild Semiconductor Corporation DS005132 www.fairchildsemi.com MM74HC32 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C 600 mW 500 mW (ICC) Storage Temperature Range (TSTG) Recommended Operating Conditions Min 2 0 Max 6 VCC Units V V −0.5 to + 7.0V −1.5 to VCC + 1.5V Supply Voltage (V ) CC −0.5 to VCC + 0.5V DC Input or Output Voltage ±20 mA ±25 mA Operating Temperature Range (T ) A ±50 mA Input Rise or Fall Times −65°C to +150°C (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V (VIN, VOUT ) −40 +85 1000 500 400 °C ns ns ns Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage (Note 4) Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V T A = 2 5 °C Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4.5 6.0 4.7 5.2 0 0 0 0.2 0.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 2.0 TA = −40 to 85°C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 20 Units V V V V V V V V V V V V V V V V µA µA VIN = VIH or VIL |IOUT | ≤ 20 µA 2.0V 4.5V 6.0V VIN = VIH or VIL | IOUT | ≤ 4.0 mA | IOUT | ≤ 5.2 mA 4.5V 6.0V 2.0V 4.5V 6.0V VIN = VIL | IOUT | ≤ 4.0 mA | IOUT | ≤ 5.2 mA 4.5V 6.0V 6.0V 6.0V VOL Maximum LOW Level Output Voltage VIN = VIL |IOUT | ≤ 20 µA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VCC or GND VIN = VCC or GND IOUT = 0 µA Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. www.fairchildsemi.com 2 MM74HC32 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol tPHL, tPLH Parameter Maximum Propagation Delay Conditions Typ 10 Guaranteed Limit 18 Units ns AC Electrical Characteristics VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol tPHL, tPLH Parameter Maximum Propagation Delay tTLH, tTHL Maximum Output Rise and Fall Time CPD CIN Power Dissipation Capacitance (Note 5) Maximum Input Capacitance Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V T A = 2 5 °C Typ 30 12 9 30 8 7 50 5 10 100 20 17 75 15 13 TA = −40 to 85°C Guaranteed Limits 125 25 21 95 19 16 Units ns ns ns ns ns ns pF (per gate) 10 pF 3 www.fairchildsemi.com MM74HC32 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 4 MM74HC32 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com MM74HC32 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 6 MM74HC32 Quad 2-Input OR Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com