MM74HC373

MM74HC373 3-STATE Octal D-Type Latch September 1983 Revised May 2005 MM74HC373 3-STATE Octal D-Type Latch General Description The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. When the LATCH ENABLE input is HIGH, the Q outputs will follow the D inputs. When the LATCH ENABLE goes LOW, data at the D inputs will be retained at the outputs until LATCH ENABLE returns HIGH again. When a high logic level is applied to the OUTPUT CONTROL input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features s Typical propagation delay: 18 ns s Wide operating voltage range: 2 to 6 volts s Low input current: 1 PA maximum s Low quiescent current: 80 PA maximum (74 Series) s Output drive capability: 15 LS-TTL loads Ordering Code: Order Number MM74HC373WM MM74HC373SJ MM74HC373MTC MM74HC373N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Truth Table Output Control L L L H Latch Enable H H L X H L X X Data 373 Output H L Q0 Z H HIGH Level L LOW Level Q0 Level of output before steady-state input conditions were established. Z High Impedance Top View © 2005 Fairchild Semiconductor Corporation DS005335 www.fairchildsemi.com MM74HC373 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN ) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260 qC 600 mW 500 mW Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN,VOUT ) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC VCC VCC 2.0V 4.5V 6.0V 1000 500 400 ns ns ns 0 VCC V 2 Max 6 Units V 0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r35 mA r70 mA 65qC to 150qC 40 85 qC Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package:  12 mW/qC from 65qC to 85qC. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN VIH or VIL 2.0V 4.5V 6.0V VIN VIH or VIL 4.5V 6.0V 2.0V 4.5V 6.0V VIN VIH or VIL 4.5V 6.0V 6.0V VIH 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V |IOUT| d 6.0 mA |IOUT| d 7.8 mA IIN IOZ Maximum Input Current Maximum 3-STATE Output Leakage Current ICC Maximum Quiescent Supply Current VIN IOUT VCC or GND 0 PA 6.0V 8.0 80 160 VIN VOUT VIH or VIL, OC VCC or GND VIN VCC or GND 4.2 5.7 0 0 0 3.98 5.48 0.1 0.1 0.1 3.84 5.34 0.1 0.1 0.1 3.7 5.2 0.1 0.1 0.1 V V V V V |IOUT| d 6.0 mA |IOUT| d 7.8 mA VOL Maximum LOW Level Output Voltage VIN VIH or VIL |IOUT| d 20 PA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V |IOUT| d 20 PA TA Typ 1.5 3.15 4.2 0.5 1.35 1.8 2 5 qC TA 40 to 85qC TA 55 to 125qC Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.5 3.15 4.2 0.5 1.35 1.8 Units V V V V V V r0.1 r0.5 r1.0 r5 r1.0 r10 PA PA PA Note 4: For a power supply of 5V r10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. www.fairchildsemi.com 2 MM74HC373 AC Electrical Characteristics VCC 5V, TA 25qC, tr t f 6 ns Parameter Conditions 45 pF 45 pF 1 k: 45 pF 1 k: 5 pF 5 10 9 16 ns ns ns 18 25 ns Typ 18 21 20 Guaranteed Limit 25 30 28 Units ns ns ns Symbol tPHL, tPLH tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tS tH tW Maximum Propagation Delay, Data to Q CL Maximum Propagation Delay, LE to Q Maximum Output Enable Time Maximum Output Disable Time Minimum Set Up Time Minimum Hold Time Minimum Pulse Width CL RL CL RL CL AC Electrical Characteristics VCC 2.06.0V, CL 50 pF, tr tf 6 ns (unless otherwise specified) Conditions CL CL CL CL CL CL 50 pF 150 pF 50 pF 150 pF 50 pF 150 pF 50 pF 150 pF 50 pF 150 pF 50 pF 150 pF 1 k: 50 pF 150 pF 50 pF 150 pF 50 pF 150 pF 1 k: 50 pF 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 50 80 21 30 19 26 50 21 19 150 200 30 40 26 35 150 30 26 50 9 9 5 5 5 30 10 9 25 7 6 30 50 5 10 10 10 80 16 14 60 12 10 188 250 37 50 31 44 188 37 31 60 13 11 5 5 5 100 20 18 75 15 13 225 300 45 60 39 53 225 45 39 75 15 13 5 5 5 120 24 20 90 18 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF pF VCC 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V TA Typ 50 80 22 30 19 26 63 110 25 35 21 28 150 200 30 40 26 35 175 225 35 45 30 39 2 5 qC TA Symbol Parameter 40 to 85qC TA 55 to 125qC Guaranteed Limits 188 250 37 50 31 44 220 280 44 56 37 49 225 300 45 60 39 53 263 338 52 68 45 59 Units ns ns ns ns ns ns ns ns ns ns ns ns tPHL, tPLH Maximum Propagation Delay, Data to Q tPHL, tPLH Maximum Propagation Delay, LE to Q CL CL CL CL CL CL tPZH, tPZL Maximum Output Enable Time RL CL CL CL CL CL CL tPHZ, tPLZ Maximum Output Disable Disable Time tS Minimum Set Up Time RL CL tH Minimum Hold Time 2.0V 4.5V 6.0V tW Minimum Pulse Width 2.0V 4.5V 6.0V tTHL, tTLH Maximum Output Rise and Fall Time CPD Power Dissipation Capacitance (Note 5) CIN Maximum Input Capacitance CL 50 pF 2.0V 4.5V 6.0V (per latch) OC OC VCC GND 3 www.fairchildsemi.com MM74HC373 AC Electrical Characteristics Symbol COUT Parameter Maximum Output Capacitance (Continued) TA Typ 15 20 2 5 qC TA Conditions VCC 40 to 85qC TA 55 to 125qC Guaranteed Limits 20 20 Units pF Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC f  ICC. CPD VCC2 f  ICC VCC, and the no load dynamic current consumption, www.fairchildsemi.com 4 MM74HC373 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com MM74HC373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 MM74HC373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com MM74HC373 3-STATE Octal D-Type Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com