MM74HC4049NX

MM74HC4049 • MM74HC4050 Hex Inverting Logic Level Down Converter • Hex Logic Level Down Converter February 1984 Revised October 1999 MM74HC4049 • MM74HC4050 Hex Inverting Logic Level Down Converter • Hex Logic Level Down Converter General Description The MM74HC4049 and the MM74HC4050 utilize advanced silicon-gate CMOS technology, and have a modified input protection structure that enables these parts to be used as logic level translators which will convert high level logic to a low level logic while operating from the low logic supply. For example, 0–15V CMOS logic can be converted to 0–5V logic when using a 5V supply. The modified input protection has no diode connected to VCC, thus allowing the input voltage to exceed the supply. The lower zener diode protects the input from both positive and negative static voltages. In addition each part can be used as a simple buffer or inverter without level translation. The MM74HC4049 is pin and functionally compatible to the CD4049BC and the MM74HC4050 is compatible to the CD4050BC Features s Typical propagation delay: 8 ns s Wide power supply range: 2V–6V s Low quiescent supply current: 20 µA maximum (74HC) s Fanout of 10 LS-TTL loads Ordering Code: Order Number MM74HC4049M MM74HC4049SJ MM74HC4049MTC MM74HC4049N MM74HC4050M MM74HC4050SJ MM74HC4050MTC MM74HC4050N Package Number Package Description M16A M16D MTC16 N16E M16A M16D MTC16 N16E 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams MM74HC4049 MM74HC4050 © 1999 Fairchild Semiconductor Corporation DS005214 www.fairchildsemi.com MM74HC4049 • MM74HC4050 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IZK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C 600 mW 500 mW −0.5 to +7.0V −1.5 to +18V −0.5 to VCC +0.5V −20 mA ±25 mA ±50 mA −65°C to +150°C Recommended Operating Conditions Min Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns −40 +85 °C 0 VCC V 2 0 Max 6 15 Units V V Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT | ≤ 20 µA Conditions (Note 4) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 TA = 25°C Typ 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 ±0.5 2.0 TA = −40°C to 85°C TA = −55°C to 125°C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 ±5 20 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 ±5 40 V V V V V V V V V V V V V V V V µA µA µA Units VIN = VIH or VIL |IOUT | ≤ 4.0 mA |IOUT | ≤ 5.2 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT | ≤ 20 µA 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT | ≤ 4 mA |IOUT | ≤ 5.2 mA IIN ICC Maximum Input Current VIN = VCC or GND VIN = 15V Maximum Quiescent Supply VIN = VCC or GND Current IOUT = 0 µA 4.5V 6.0V 6.0V 2.0V 6.0V 4.5V 6.0V Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. www.fairchildsemi.com 2 MM74HC4049 • MM74HC4050 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol tPHL, tPLH Parameter Maximum Propagation Delay Conditions Typ 8 Guaranteed Limit 15 Units ns AC Electrical Characteristics VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol tPHL, tPLH Parameter Maximum Propagation Delay tTHL, tTLH Maximum Output Rise and Fall Time CPD CIN Power Dissipation Capacitance (Note 5) Maximum Input Capacitance Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA = 25°C Typ 30 10 9 25 7 6 25 5 10 85 17 15 75 15 13 TA = −40° to 85°C TA = −55° to 125°C Guaranteed Limits 100 20 18 95 19 16 130 26 22 110 22 19 Units ns ns ns ns ns ns pF (per gate) 10 10 pF 3 www.fairchildsemi.com MM74HC4049 • MM74HC4050 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 4 MM74HC4049 • MM74HC4050 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 5 www.fairchildsemi.com MM74HC4049 • MM74HC4050 Hex Inverting Logic Level Down Converter • Hex Logic Level Down Converter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com