MM74HC4514_03

MM74HC4514 4-to-16 Line Decoder with Latch February 1984 Revised July 2003 MM74HC4514 4-to-16 Line Decoder with Latch General Description The MM74HC4514 utilizes advanced silicon-gate CMOS technology, which is well suited to memory address decoding or data routing application. It possesses high noise immunity and low power dissipation usually associated with CMOS circuitry, yet speeds comparable to low power Schottky TTL circuits. It can drive up to 10 LS-TTL loads. The MM74HC4514 contain a 4-to-16 line decoder and a 4bit latch. The latch can store the data on the select inputs, thus allowing a selected output to remain HIGH even though the select data has changed. When the LATCH ENABLE input to the latches is HIGH the outputs will change with the inputs. When LATCH ENABLE goes LOW the data on the select inputs is stored in the latches. The four select inputs determine which output will go HIGH provided the INHIBIT input is LOW. If the INHIBIT input is HIGH all outputs are held LOW thus disabling the decoder. The MM74HC4514 is functionally and pinout equivalent to the CD4514BC and the MC1451BC. All inputs are protected against damage due to static discharge diodes from VCC and ground. Features s Typical propagation delay: 18 ns s Low quiescent power: 80 µA maximum (74HC Series) s Low input current: 1 µA maximum s Fanout of 10 LS-TTL loads (74HC Series) Ordering Code: Order Number MM74HC4514WM MM74HC4514MTC MM74HC4514N Package Number M24B MTC24 N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2003 Fairchild Semiconductor Corporation DS005215 www.fairchildsemi.com MM74HC4514 Connection Diagram Truth Table Data Inputs LE Inhibit D C B A Selected Output High S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 All X L H L X X X X X X X X Outputs = 0 Latched Data H H H H H H H H H H H H H Top View H H H L L L L L L L L L L L L L L L L L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H Logic Diagram www.fairchildsemi.com 2 MM74HC4514 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C 600 mW 500 mW Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns 2 0 Max 6 VCC Units V V −0.5 to +7.0V −1.5 to VCC +1.5V −0.5 to VCC +0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C −40 +85 °C Note 1: M aximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT | ≤ 20 µA VIN = VIH or VIL |IOUT | ≤ 4.0 mA |IOUT | ≤ 5.2 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT | ≤ 20 µA VIN = VIH or VIL |IOUT | ≤ 4.0 mA |IOUT | ≤ 5.2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VCC or GND VIN = VCC or GND IOUT = 0 µA Conditions (Note 4) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 4.5V 6.0V 2.0V 4.5V 6.0V 4.5V 6.0V 6.0V 6.0V 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 TA = 25°C Typ 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 8.0 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 80 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 160 µA µA V V V V V V Units Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC4514 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol tPHL, tPLH tPHL tPLH tPHL tPLH ts tH tW Parameter Maximum Propagation Delay Data to Output Maximum Propagation Delay LE to Output Maximum Propagation Delay LE to Output Maximum Propagation Delay Inhibit to Output Maximum Propagation Delay Inhibit to Output Minimum Setup Time, Date to LE Minimum Hold Time, LE to Data Minimum Pulse Width, Latch Enable Conditions Typ 18 18 24 16 24 Guaranteed Limit 30 30 40 30 40 20 5 16 Units ns ns ns ns ns ns ns ns AC Electrical Characteristics VCC = 2.0V − 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC 2.0V 4.5V 6.0V tPHL Maximum Propagation Delay LE to Output tPLH Maximum Propagation Delay LE to Output tPHL Maximum Propagation Delay Inhibit to Output tPLH Maximum Propagation Delay Inhibit to Output ts Minimum Setup Time, Data to LE tH Minimum Hold Time, LE to Data tW Minimum Pulse Width, Latch Enable CPD CIN Power Dissipation Capacitance (Note 5) Maximum Input Capacitance 2 TA = 25°C Typ 80 18 16 80 19 17 120 27 22 70 18 16 120 27 22 175 35 30 175 35 30 230 46 39 175 35 30 230 46 39 100 20 17 5 5 5 80 16 14 290 5 10 TA= −40 to 85°C TA = −55 to 125°C Guaranteed Limits 220 44 38 220 44 38 290 58 49 220 44 38 290 58 49 125 25 21 5 5 5 100 20 17 263 53 45 263 53 45 343 69 58 263 53 45 343 69 58 150 30 25 5 5 5 120 24 20 Units tPHL, tPLH Maximum Propagation Delay Data to Output ns 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V ns ns ns ns ns ns ns pF 10 10 pF Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + I CC. www.fairchildsemi.com 4 MM74HC4514 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B 5 www.fairchildsemi.com MM74HC4514 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 www.fairchildsemi.com 6 MM74HC4514 4-to-16 Line Decoder with Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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