MM74HC589M

MM74HC589 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output September 1983 Revised September 2001 MM74HC589 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output General Description The MM74HC589 high speed shift register utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. The MM74HC589 comes in a 16-pin package and consists of an 8-bit storage latch feeding a parallel-in, serial-out 8bit shift register. Data can also be entered serially the shift register through the SER pin. Both the storage register and shift register have positive-edge triggered clocks, RCK and SCK, respectively. SLOAD pin controls parallel LOAD or serial shift operations for the shift register. The shift register has a 3-STATE output to enable the wire-ORing of multiple devices on a serial bus. The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features s 8-bit parallel storage register inputs s Wide operating voltage range: 2V–6V s Shift register has direct overriding load s Guaranteed shift frequency. . . DC to 30 MHz s Low quiescent current: 80 µA maximum (74HC Series) s 3-STATE output for ‘Wire-OR' Ordering Code: Order Number MM74HC589M MM74HC589SJ MM74HC589N Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table RCK SCK SLOAD OE X X X X X X X X X L H L X X Function QH in Hi-Z State QH is enabled Data loaded into input latches Data loaded into shift register from pins H or L X L X Data loaded from latches to shift register X ↑ ↑ Top View ↑ ↑ H X Shift register is shifted. Data on SER pin is shifted in. ↑ H X Data is shifted in shift register, and data is loaded into latches © 2001 Fairchild Semiconductor Corporation DS005368 www.fairchildsemi.com MM74HC589 Block Diagram (positive logic) www.fairchildsemi.com 2 MM74HC589 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C 600 mW 500 mW Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT ) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns 0 VCC V 2 Max 6 Units V −0.5 to +7.0V −1.5 to VCC +1.5V −0.5 to VCC +0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C −40 +85 °C Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA Conditions (Note 4) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0 4.5 6.0 TA = 25°C Typ 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0 0 0 0.1 0.1 0.1 0.26 0.26 ±0.1 8.0 ±0.5 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 80 ±5.0 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 160 ±10.0 Units V V V V V V V V V V V V V V V V µA µA µA VIN = VIH or VIL |IOUT| ≤ 6.0 mA |IOUT| ≤ 7.8 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| ≤ 6.0 mA |IOUT| ≤ 7.8 mA IIN ICC IOZ Maximum Input Current Maximum Quiescent Supply Current Maximum 3-STATE Leakage Current VIN = VCC or GND IOUT = 0 µA Output in High Impedance State VIN = VIL or VIH VOUT = VCC or GND OE = VIH Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 4.5V 6.0V 4.5V 6.0V 6.0V 6.0V 6.0V VIN = VCC or GND 3 www.fairchildsemi.com MM74HC589 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol Parameter fMAX tPHL, tPLH tPHL, tPLH tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tS tS tS tH tW Maximum Operating Frequency for SCK Maximum Propagation Delay from SCK to QH’ Maximum Propagation Delay from SLOAD to QH’ Maximum Propagation Delay from LCK to QH’ Output Enable Time Output Disable Time Minimum Setup Time from RCK to SCK Minimum Setup Time from SER to SCK Minimum Setup Time from Inputs A thru H to RCK Minimum Hold Time Minimum Pulse Width SCK, RCK, SLOAD SLOAD = logic “0” RL = 1 kΩ RL = 1 kΩ, CL = 5 pF 25 18 19 10 10 10 0 8 Conditions Typ 50 Guaranteed Limit 30 30 30 45 28 25 20 20 20 5 16 Units MHz ns ns ns ns ns ns ns ns ns ns AC Electrical Characteristics VCC = 2.0−6V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Operating Frequency for SCK tPHL, tPLH Maximum Propagation Delay from SCK or SLOAD to QH tPHL, tPLH Maximum Propagation Delay from SCK or SLOAD to QH tPHL, tPLH Maximum Propagation Delay from RCK to QH tPHL, tPLH Maximum Propagation Delay RCK to QH tPZH, tPZL Output Enable Time CL = 150 pF RL = 1 kΩ CL = 150 pF Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V tPHZ, tPLZ Output Disable Time RL = 1 kΩ 2.0V 4.5V 6.0V tS Minimum Setup Time from RCK to SCK tS Minimum Setup Time from SER to SCK tS Minimum Setup Time from Inputs A thru H to RCK tH Minimum Hold Time 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V tW Minimum Pulse Width SCK, RCK, SLOAD, SLOAD 2.0V 4.5V 6.0V −5 0 1 30 9 8 62 20 18 120 31 28 80 25 21 80 25 21 70 22 20 70 22 20 T A = 2 5 °C Typ 6 30 35 175 35 30 225 45 38 210 42 36 210 52 44 150 30 26 150 30 26 100 20 17 100 20 17 100 20 17 5 5 5 80 16 14 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 4.8 24 28 220 44 37 280 56 48 265 53 45 265 66 56 189 38 32 189 38 32 125 25 22 125 25 22 125 25 22 5 5 5 100 20 17 4 20 24 265 53 45 340 68 58 315 63 54 313 77 66 224 45 38 224 45 38 150 30 25 150 30 25 150 30 25 5 5 5 120 24 20 Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns www.fairchildsemi.com 4 MM74HC589 AC Electrical Characteristics Symbol tr, tf Parameter Maximum Input Rise and Fall Time, Clock tTHL, tTLH Maximum Output Rise and Fall Time CPD CIN COUT Power Dissipation Capacitance (Note 5) Maximum Input Capacitance Maximum Output Capacitance (Continued) TA = 25°C Typ 1500 500 400 25 6 5 87 5 15 10 20 10 20 10 20 60 12 10 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 1500 500 400 75 15 12 1500 500 400 90 18 15 ns ns ns ns ns ns pF pF pF Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V Units Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC sf + ICC. 5 www.fairchildsemi.com MM74HC589 Timing Diagram www.fairchildsemi.com 6 MM74HC589 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 7 www.fairchildsemi.com MM74HC589 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 8 MM74HC589 8-Bit Shift Registers with Input Latches and 3-STATE Serial Output Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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