MM74HC595MTC

MM74HC595 8-Bit Shift Registers with Output Latches September 1983 Revised July 2004 MM74HC595 8-Bit Shift Registers with Output Latches General Description The MM74HC595 high speed shift register utilizes advanced silicon-gate CMOS technology. This device possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features s Low quiescent current: 80 µA maximum (74HC Series) s Low input current: 1 µA maximum s 8-bit serial-in, parallel-out shift register with storage s Wide operating voltage range: 2V–6V s Cascadable s Shift register has direct clear s Guaranteed shift frequency: DC to 30 MHz Ordering Code: Order Number MM74HC595M MM74HC595SJ MM74HC595MTC MM74HC595N Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table RCK X X SCK X X SCLR X L G H L Function QA thru QH = 3-STATE Shift Register cleared Q’H = 0 X ↑ H L Shift Register clocked QN = Qn-1, Q0 = SER ↑ X H L Contents of Shift Register transferred to output latches Top View © 2004 Fairchild Semiconductor Corporation DS005342 www.fairchildsemi.com MM74HC595 Logic Diagram (positive logic) www.fairchildsemi.com 2 MM74HC595 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C (Note 4) VCC 2.0V 4.5V 6.0V VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA 2.0V 4.5V 6.0V Q’H VIN = VIH or VIL |IOUT| ≤ 4.0 mA |IOUT| ≤ 5.2 mA QA thru QH VIN = VIH or VIL |IOUT| ≤ 6.0 mA |IOUT| ≤ 7.8 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA 2.0V 4.5V 6.0V Q’H VIN = VIH or VIL |IOUT| ≤ 4 mA |IOUT| ≤ 5.2 mA QA thru QH VIN = VIH or VIL |IOUT| ≤ 6.0 mA |IOUT| ≤ 7.8 mA IIN IOZ ICC Maximum Input Current Maximum 3-STATE Output Leakage Maximum Quiescent Supply Current VOUT = VCC or GND G = V IH VIN = VCC or GND IOUT = 0 µA 6.0V 6.0V VIN = VCC or GND 4.5V 6.0V 6.0V 4.5V 6.0V 4.5V 6.0V 4.5V 6.0V 2.0V 4.5V 6.0V Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 0 VCC V 2 Max 6 Units V −0.5 to +7.0V −1.5 to VCC +1.5V −0.5 to VCC +0.5V ±20 mA ±35 mA ±70 mA −65°C to +150°C 600 mW 500 mW −40 +85 1000 500 400 °C ns ns ns Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage Conditions TA = 25°C Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4.5 6.0 4.2 5.2 4.2 5.7 0 0 0 0.2 0.2 0.2 0.2 1.9 4.4 5.9 3.98 5.48 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.26 0.26 ±0.1 ±0.5 8.0 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 3.84 5.34 0.1 0.1 0.1 0.33 0.33 0.33 0.33 ±1.0 ±5.0 80 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.4 0.4 ±1.0 ±10 160 Units V V V V V V V V µA µA µA Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC595 AC Electrical Characteristics VCC = 5V, TA = 25°C, tr = tf = 6 ns Symbol fMAX tPHL, tPLH tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tS tS tS Parameter Maximum Operating Frequency of SCK Maximum Propagation Delay, SCK to Q’H Maximum Propagation Delay, RCK to QA thru QH Maximum Output Enable Time from G to QA thru QH Maximum Output Disable Time from G to QA thru QH Minimum Setup Time from SER to SCK Minimum Setup Time from SCLR to SCK Minimum Setup Time from SCK to RCK (Note 5) tH tW Minimum Hold Time from SER to SCK Minimum Pulse Width of SCK or RCK Note 5: This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be connected together in which case the storage register state will be one clock pulse behind the shift register. Conditions Typ 50 Guaranteed Limit 30 20 30 Units MHz ns ns CL = 45 pF CL = 45 pF RL = 1 kΩ CL = 45 pF RL = kΩ CL = 5 pF 12 18 17 15 28 25 20 20 40 ns ns ns ns ns 0 16 ns ns AC Electrical Characteristics VCC = 2.0−6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Operating Frequency tPHL, tPLH Maximum Propagation Delay from SCK to Q’H CL = 50 pF CL = 150 pF CL = 50 pF CL = 150 pF CL = 50 pF CL = 150 pF tPHL, tPLH Maximum Propagation CL = 50 pF CL = 50 pF CL = 150 pF CL = 50 pF CL = 150 pF tPHL, tPLH Maximum Propagation Delay from SCLR to Q’H tPZH, tPZL Maximum Output Enable from G to QA thru QH R L = 1 kΩ CL = 50 pF CL = 150 pF CL = 50 pF CL = 150 pF CL = 50 pF CL = 150 pF 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V 75 100 15 20 13 17 175 245 35 49 30 42 220 306 44 61 37 53 265 368 53 74 45 63 ns ns ns Delay from RCK to QA thru QH CL = 150 pF Conditions CL = 50 pF VCC 2.0V 4.5V 6.0V 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V 2.0V 4.5V 6.0V TA = 25°C Typ 10 45 50 58 83 14 17 10 14 70 105 21 28 18 26 6 30 35 210 294 42 58 36 50 175 245 35 49 30 42 175 35 30 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 4.8 24 28 265 367 53 74 45 63 220 306 44 61 37 53 221 44 37 4.0 20 24 315 441 63 88 54 76 265 368 53 74 45 63 261 52 44 ns ns ns ns ns ns ns MHz Units www.fairchildsemi.com 4 MM74HC595 AC Electrical Characteristics Symbol Parameter (Continued) TA = 25°C Typ 75 15 13 175 35 30 100 20 17 50 10 9 100 20 17 5 5 5 30 9 8 80 16 14 1000 500 400 25 7 6 60 12 10 75 15 13 90 150 5 15 10 20 10 20 10 20 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 220 44 37 125 25 21 63 13 11 125 25 21 5 5 5 100 20 18 1000 500 400 75 15 13 95 19 16 265 53 45 150 30 25 75 15 13 150 30 26 5 5 5 120 24 22 1000 500 400 90 18 15 110 22 19 pF ns ns ns ns ns ns ns ns ns Conditions RL = 1 kΩ CL = 50 pF VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V Units tPHZ, tPLZ Maximum Output Disable Time from G to QA thru QH tS Minimum Setup Time from SER to SCK tR Minimum Removal Time from SCLR to SCK tS Minimum Setup Time from SCK to RCK tH Minimum Hold Time SER to SCK tW Minimum Pulse Width of SCK or SCLR tr, tf Maximum Input Rise and Fall Time, Clock tTHL, tTLH Maximum Output Rise and Fall Time QA–QH tTHL, tTLH Maximum Output Rise & Fall Time Q'H CPD Power Dissipation Capacitance, Outputs Enabled (Note 6) CIN COUT Maximum Input Capacitance Maximum Output Capacitance G = VCC G = GND pF pF Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. 5 www.fairchildsemi.com MM74HC595 Timing Diagram www.fairchildsemi.com 6 MM74HC595 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 7 www.fairchildsemi.com MM74HC595 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 8 MM74HC595 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 9 www.fairchildsemi.com MM74HC595 8-Bit Shift Registers with Output Latches Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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