MM74HC597

MM74HC597 8-Bit Shift Registers with Input Latches January 1988 Revised January 2004 MM74HC597 8-Bit Shift Registers with Input Latches General Description This high speed register utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 10 LS-TTL loads. The MM74HC597 comes in a 16-pin package and consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. the shift register also has direct load (from storage) and clear inputs. The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features s 8-bit parallel storage register inputs s Wide operating voltage range: 2V–6V s Shift register has direct overriding load and clear s Guaranteed shift frequency: DC to 30 MHz s Low quiescent current: 80 µA maximum Ordering Code: Order Number MM74HC597M (Note 1) MM74HC597SJ MM74HC597N Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Note 1: D evices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table RCK SCK SLOAD SCLR Function Data Loaded to input latches Data loaded from inputs to shift register Data transferred from X L H input latches to shift register Invalid logic, state of X X X X X L H H L L H shift register indeterminate when signals removed Shift register cleared Shift register clocked Qn = Qn−1, Q 0 = SER ↑ ↑ No clock edge X X X L X H ↑ Top View © 2004 Fairchild Semiconductor Corporation DS005343 www.fairchildsemi.com MM74HC597 Functional Block Diagram (Positive Logic) Timing Diagram www.fairchildsemi.com 2 MM74HC597 Absolute Maximum Ratings(Note 2) (Note 3) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 4) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C 600 mW 500 mW Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns 0 VCC V 2 Max 6 Units V −0.5 to +7.0V −1.5 to VCC +1.5V −0.5 to VCC +0.5V ±20 mA ±25 mA ±70 mA −65°C to +150°C −40 +85 °C Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 3: Unless otherwise specified all voltages are referenced to ground. Note 4: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage (Note 6) VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA Conditions (Note 5) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0 4.5 6.0 4.2 5.2 0 0 0 0.2 0.2 TA = 25°C Typ 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 8.0 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 80 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 160 µA µA V V V V Units V VIN = VIH or VIL |IOUT| ≤ 4.0 mA |IOUT| ≤ 5.2 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| ≤ 4 mA |IOUT| ≤ 5.2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VCC or GND VIN = VCC or GND IOUT = 0 µA 4.5V 6.0V 6.0V 6.0V V 4.5V 6.0V Note 5: For a power supply of 5V ± 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. Note 6: VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY'89. 3 www.fairchildsemi.com MM74HC597 AC Electrical Characteristics Symbol fMAX tPHL tPLH tPHL tPLH tPHL tPLH tPHL tREM tS tS tS Parameter Maximum Operating Frequency of SCK Maximum Propagation Delay from SCK to QH Maximum Propagation Delay from SLOAD to QH Maximum propagation Delay from RCK to QH Maximum Propagation Delay from SCLR to QH Minimum Removal Time, SCLR to SCK Minimum Setup Time from RCK to SCK Minimum Setup Time from SER to SCK Minimum Setup Time from inputs A thru H to RCK tH tW Minimum Hold Time Minimum Pulse Width SCK, RCK, SCLR SLOAD VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Conditions Typ 50 20 20 Guaranteed Limit 30 30 30 Units MHz ns ns SLOAD = logic “0” 25 20 10 30 10 45 30 20 40 20 ns ns ns ns ns 10 −2 10 20 0 16 ns ns ns AC Electrical Characteristics Symbol fMAX Parameter Maximum Operating Frequency tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum Propagation Delay from SCK to QH Maximum Propagation Delay from SLOAD to QH Maximum Propagation Delay from RCK to QH Maximum Propagatin Delay from SCLR to QH tREM Minimum Removal Time SCLR to SCK tS Minimum Setup Time from RCK to SCK tS Minimum Setup Time from SER to SCK VCC = 2.0–6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V TA = 25°C Typ 10 45 50 62 20 18 65 20 18 120 30 28 66 20 18 6.0 30 35 175 35 30 175 35 30 205 41 35 175 35 30 100 20 17 200 40 34 100 20 17 TA=−40 to 85°C TA=−55 to 125°C Guaranteed Limits 4.8 24 28 220 44 38 220 44 38 255 51 43 220 44 38 125 25 21 250 50 42 125 25 21 4.0 20 24 263 53 45 263 53 45 310 62 53 263 53 45 150 30 25 300 60 50 150 30 25 ns ns ns ns ns ns ns MHz Units Conditions SLOAD = Logic “0” 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V www.fairchildsemi.com 4 MM74HC597 AC Electrical Characteristics Symbol tS Parameter Minimum Setup Time from Inputs A thru H to RCK tH Minimum Hold Time (Continued) TA = 25°C Typ 100 20 17 0 0 0 30 9 8 80 16 14 1000 500 400 30 10 8 75 15 13 75 15 13 87 5 15 2 Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA=−40 to 85°C TA=−55 to 125°C Guaranteed Limits 125 25 21 0 0 0 100 20 18 1000 500 400 95 19 16 95 19 16 150 30 25 0 0 0 120 24 20 1000 500 400 110 22 19 110 22 19 Units ns ns tW Minimum Pulse Width SCK, RCK, SCLR, SLOAD 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V ns tr, tf Maximum Input Rise and Fall Time ns tTHL, tTLH Maximum Output Rise and Fall Time ns tTHL, tTLH Maximum Output Rise and Fall Time ns CPD CIN COUT Power Dissipation Capacitance, Outputs (Note 7) Maximum Input Capacitance Maximum Output Capacitance pF 10 20 10 20 10 20 pF pF Note 7: CPD determines the no load dynamic power consumption, PD = CPD VCC f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. 5 www.fairchildsemi.com MM74HC597 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A www.fairchildsemi.com 6 MM74HC597 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com MM74HC597 8-Bit Shift Registers with Input Latches Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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