MM74HCT00MTCX_NL

MM74HCT00 Quad 2 Input NAND Gate February 1984 Revised January 2005 MM74HCT00 Quad 2 Input NAND Gate General Description The MM74HCT00 is a NAND gates fabricated using advanced silicon-gate CMOS technology which provides the inherent benefits of CMOS—low quiescent power and wide power supply range. This device is input and output characteristic and pin-out compatible with standard 74LS logic families. All inputs are protected from static discharge damage by internal diodes to VCC and ground. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. Features s TTL, LS pin-out and threshold compatible s Fast switching: tPLH, tPHL=14 ns (typ) s Low power: 10 µW at DC s High fan out, 10 LS-TTL loads Ordering Code: Order Number MM74HCT00M MM74HCT00MX_NL MM74HCT00SJ MM74HCT00MTC MM74HCT00MTCX_NL MM74HCT00N MM74HCT00N_NL Package Number M14A M14A M14D MTC14 MTC14 N14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Logic Diagram (1 of 4 gates) Top View © 2005 Fairchild Semiconductor Corporation DS005356 www.fairchildsemi.com MM74HCT00 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C 600 mW 500 mW Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) 500 ns Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. −0.5 to +7.0V −1.5 to VCC+1.5V −0.5 to VCC+0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C Max 5.5 VCC Units V V 4.5 0 −40 +85 °C DC Electrical Characteristics VCC = 5V ± 10% (unless otherwise specified) Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| = 20 µA |IOUT| = 4.0 mA, VCC = 4.5V |IOUT| = 4.8 mA, VCC = 5.5V VOL Maximum LOW Level Voltage VIN = VIH |IOUT| = 20 µA |IOUT| = 4.0 mA, VCC = 4.5V |IOUT| = 4.8 mA, VCC = 5.5V IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VCC or GND, VIH or VIL VIN = VCC or GND, IOUT = 0 µA VIN = 2.4V or 0.5V (Note 4) Note 4: This is measured per input with all other inputs held at VCC or ground. Conditions TA = 25°C Typ 2.0 0.8 TA = −40 to 85°C TA = -55 to 125°C Guaranteed Limits 2.0 0.8 2.0 0.8 Units V V VCC 4.2 5.2 0 0.2 0.2 VCC−0.1 3.98 4.98 0.1 0.26 0.26 ±0.05 1.0 VCC−0.1 3.84 4.84 0.1 0.33 0.33 ±0.5 10 0.4 VCC−0.1 3.7 4.7 0.1 0.4 0.4 ±1.0 40 0.5 V V V V V V µA µA mA 0.18 0.3 www.fairchildsemi.com 2 MM74HCT00 AC Electrical Characteristics VCC = 5.0V, tr = tr = 6 ns, CL = 15 pF, TA = 25°C (unless otherwise noted) Symbol tPLH, tPHL Parameter Maximum Propagation Delay Conditions Typ 14 Guaranteed Limit 18 Units ns AC Electrical Characteristics VCC = 5.0V ±10%, tr = tf = 6 ns, CL = 50 pF (unless otherwise noted) Symbol tPLH, tPHL tTHL, tTLH CPD CIN Parameter Maximum Propagation Delay Maximum Output Rise & Fall Time Power Dissipation Capacitance Input Capacitance (Note 5) Conditions T A = 2 5 °C Typ 18 8 30 5 10 10 10 23 15 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 29 19 35 22 Units ns ns pF pF Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. 3 www.fairchildsemi.com MM74HCT00 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 4 MM74HCT00 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com MM74HCT00 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 6 MM74HCT00 Quad 2 Input NAND Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com