NDC652P

March 1996 NDC652P P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. Features -2.4A, -30V. RDS(ON) = 0.18Ω @ VGS = -4.5V RDS(ON) = 0.11Ω @ VGS = -10V. Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. ____________________________________________________________________________________________ 4 3 5 2 6 1 Absolute Maximum Ratings Symbol Parameter VDSS VGSS ID PD Drain-Source Voltage Gate-Source Voltage - Continuous Drain Current - Continuous - Pulsed Maximum Power Dissipation T A = 25°C unless otherwise noted NDC652P -30 -20 -2.4 -10 (Note 1a) (Note 1b) (Note 1c) Units V V A 1.6 1 0.8 -55 to 150 W TJ,TSTG Operating and Storage Temperature Range °C THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 78 30 °C/W °C/W © 1997 Fairchild Semiconductor Corporation NDC652P Rev. D1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS IGSSF IGSSR VGS(th) RDS(ON) Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = -250 µA VDS = -24 V, VGS = 0 V TJ = 55oC Gate - Body Leakage, Forward Gate - Body Leakage, Reverse VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V VDS = VGS, ID = -250 µA TJ = 125oC Static Drain-Source On-Resistance VGS = -4.5 V, ID = -2.4 A TJ = 125oC VGS = -10 V, ID = -3.1 A ID(on) gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd On-State Drain Current Forward Transconductance VGS = -4.5 V, VDS = -5 V VDS = -10 V, ID = -2.4 A VDS = -15 V, VGS = 0 V, f = 1.0 MHz -5 3 -1 -0.7 -1.5 -1.2 0.16 0.22 0.09 -30 1 10 100 -100 V µA µA nA nA ON CHARACTERISTICS (Note 2) Gate Threshold Voltage -3 -2.2 0.18 0.36 0.11 A S V Ω DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance 290 180 60 pF pF pF SWITCHING CHARACTERISTICS (Note 2) Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = -15 V, ID = -2.4 A, VGS = -10 V VDD = -15 V, ID = -1 A, VGEN = -4.5 V, RGEN = 6 Ω 13 26 22 19 10.5 1.5 3.3 20 35 30 30 20 ns ns ns ns nC nC nC NDC652P Rev. D1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS IS VSD Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. Continuous Source Diode Current Drain-Source Diode Forward Voltage VGS = 0 V, IS = -1.3 A (Note 2) -0.8 -1.3 -1.2 A V P D (t ) = R θJ At ) ( T J−TA = R θJ C RθCA t ) + ( T J−TA = I 2 (t ) × RDS(ON ) D TJ Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 78oC/W when mounted on a 1 in2 pad of 2oz cpper. b. 125oC/W when mounted on a 0.01 in2 pad of 2oz cpper. c. 156oC/W when mounted on a 0.003 in2 pad of 2oz cpper. 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDC652P Rev. D1 Typical Electrical Characteristics -10 2.5 V GS I D , DRAIN-SOURCE CURRENT (A) -8 = -10V DRAIN-SOURCE ON-RESISTANCE -7.0 - 6.0 - 5.5 - 5.0 - 4.5 R DS(ON), NORMALIZED V GS = -3.0V 2 - 3.5 - 4.0 -6 - 4.0 1.5 - 4.5 - 5.0 -4 - 3.5 1 -2 - 3.0 - 2.5 - 5.5 - 6.0 - 7.0 - 10 0 -2 -4 -6 ID , DRAIN CURRENT (A) -8 -10 0 0 -0.5 V DS -1 -1.5 -2 -2.5 , DRAIN-SOURCE VOLTAGE (V) -3 0.5 Figure 1. On-Region Characteristics Figure 2. On-Resistance Variation with Drain Current and Gate Voltage 1.6 2.5 DRAIN-SOURCE ON-RESISTANCE 1.4 V GS = -4.5V R DS(on) NORMALIZED , DRAIN-SOURCE ON-RESISTANCE I D = -2.4A V G S = - 4.5 V 2 R DS(ON), NORMALIZED 1.2 T J = 125°C 1.5 1 2 5°C 0.8 1 - 55°C 0.6 -50 -25 0 25 50 75 100 125 150 0.5 0 -2 -4 -6 I D , DRAIN CURRENT (A) -8 -10 T J , JUNCTION TEMPERATURE (°C) Figure 3. On-Resistance Variation with Temperature Figure 4. On-Resistance Variation with Drain Current and Temperature -10 1.2 T J = -55°C V th, NORMALIZED GATE-SOURCE THRESHOLD VOLTAGE V DS = - 10V -8 125°C 1.1 V DS = V I D GS = -250µA I D , DRAIN CURRENT (A) 25°C -6 1 0.9 -4 0.8 -2 0.7 0 -1 -2 -3 -4 -5 V GS , GATE TO SOURCE VOLTAGE (V) -6 0.6 -50 -25 0 25 50 75 100 T J , JUNCTION TEMPERATURE (°C) 125 150 Figure 5. Transfer Characteristics Figure 6. Gate Threshold Variation with Temperature NDC652P Rev. D1 Typical Electrical Characteristics (continued) 1.1 10 DRAIN-SOURCE BREAKDOWN VOLTAGE I D = -250µA -I S , REVERSE DRAIN CURRENT (A) 1.08 1.06 1.04 1.02 1 0.98 0.96 0.94 -50 5 VG S = 0V T J = 125°C 25°C - 55°C 1 BV DSS , NORMALIZED 0.1 0.01 -25 0 25 50 75 100 T J , JUNCTION TEMPERATURE (°C) 125 150 0.001 0.2 0.4 0.6 0.8 1 -V SD , BODY DIODE FORWARD VOLTAGE (V) 1.2 Figure 7. Breakdown Voltage Variation with Temperature Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature 1000 10 I D = -2.4A -V GS , GATE-SOURCE VOLTAGE (V) 500 CAPACITANCE (pF) 8 V DS = -5V -15V -10V C i ss C o ss 200 6 4 100 f = 1 MHz V GS = 0 V C r ss 2 50 0.1 0.2 -V DS 0.5 1 2 5 10 , DRAIN TO SOURCE VOLTAGE (V) 30 0 0 2 4 6 8 10 12 Q g , GATE CHARGE (nC) Figure 9. Capacitance Characteristics Figure 10. Gate Charge Characteristics -VDD t d(on) t on t off tr 90% t d(off) 90% tf V IN D RL V OUT VOUT 10% VGS R GEN 10% 90% G DUT S V IN 10% 50% 50% PULSE WIDTH INVERTED Figure 11. Switching Test Circuit Figure 12. Switching Waveforms NDC652P Rev. D1 Typical Electrical and ThermalCharacteristics (continued) 8 STEADY-STATE POWER DISSIPATION (W) 2 , TRANSCONDUCTANCE (SIEMENS) V DS = -10V 6 1a TJ = -55°C 2 5°C 1.5 4 1 25°C 1 1b 1c 2 0.5 4.5"x5" FR-4 Board TA = 2 5 C Still Air o g FS 0 0 -2 -4 -6 -8 -10 I D , DRAIN CURRENT (A) 0 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 Figure 13. Transconductance Variation with Drain Current and Temperature Figure 14. SOT-6 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. 3 -I D , STEADY-STATE DRAIN CURRENT (A) 30 10 2.5 1a -I D, DRAIN CURRENT (A) 3 RD S( O L N) IM IT 1 2 1b 1c 10 1s 10 0u s 1m s 10 ms 0m s 0.3 V 0.1 GS = -4.5V DC 1.5 4.5"x5" FR-4 Board TA = 2 5 C Still Air VG S = - 4 . 5 V o SINGLE PULSE R θJ A = See Note 1c T A = 25°C 0.2 0.5 1 2 5 10 -VDS , DRAIN-SOURCE VOLTAGE (V) 30 50 0.03 0.01 0.1 1 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 Figure 15. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. Figure 16. Maximum Safe Operating Area 1 TRANSIENT THERMAL RESISTANCE 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.00001 0.0001 0.001 0.01 0.1 t 1 , TIME (sec) 1 10 100 300 D = 0 .5 r(t), NORMALIZED EFFECTIVE 0 .2 0 .1 0 .05 0 .02 0 .01 S ingle Pulse P(pk) R θJA (t) = r(t) * R θJA R JA = See Note 1c θ t1 TJ - T A t2 =P *R (t) θJA D uty Cycle, D = t 1 / t 2 Figure 17. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDC652P Rev. D1 SuperSOTTM-6 Tape and Reel Data and Package Dimensions SSOT-6 Packaging Configuration: Figur e 1.0 Packaging Description: Customize Label Anti static Cover Tape SSOT-6 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 3,000 units per 7" or 177cm diameter reel. The reels are dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 10,000 units per 13" or 330cm diameter reel. This and some other options are described in the Packaging Information table. These full reels are individually barcode labeled and placed inside a pizza box (illustrated in figure 1.0) made of recyclable corrugated brown paper with a Fairchild logo printing. One pizza box contains three reels maximum. And these pizza boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped. F63TNR Label Embossed Carrier Tape 631 631 SSOT-6 Packaging Information Packaging Option Packaging type Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Max qty per Box Weight per unit (gm) Weight per Reel (kg) Note/Comments Standard (no f l ow c ode ) 631 631 631 Pin 1 D87Z TNR 10,000 13" 343x343x64 30,000 0.0158 0.4700 TNR 3,000 7" Dia 184x187x47 9,000 0.0158 0.1440 SSOT-6 Unit Orientation 343mm x 342mm x 64mm Intermediate box fo r D87Z Option F63TNR Label F63TNR Label F63TNR Label sa mpl e 184mm x 187mm x 47mm Pizza Box fo r Standar d Opti on F63TNR Label LOT: CBVK741B019 FSID: FDC633N QTY: 3000 SPEC: SSOT-6 Tape Leader and Trailer Configuration: Figur e 2.0 D/C1: D9842 D/C2: QTY1: QTY2: SPEC REV: CPN: N/F: F (F63TNR)3 Carrier Tape Cover Tape Comp onent s Traile r Tape 300mm mi nimum or 75 empty poc kets Lead er Tape 500mm mi nimum or 125 emp ty poc kets 1998 Fairchild Semiconductor Corporation August 1999, Rev. C SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued SSOT-6 Embossed Carrier Tape Configuration: Figure 3.0 T E1 P0 D0 F K0 Wc B0 E2 W Tc A0 P1 D1 User Direction of Feed Dimensions are in millimeter Pkg type SSOT-6 (8mm) A0 3.23 +/-0.10 B0 3.18 +/-0.10 W 8.0 +/-0.3 D0 1.55 +/-0.05 D1 1.125 +/-0.125 E1 1.75 +/-0.10 E2 6.25 min F 3.50 +/-0.05 P1 4.0 +/-0.1 P0 4.0 +/-0.1 K0 1.37 +/-0.10 T 0.255 +/-0.150 Wc 5.2 +/-0.3 Tc 0.06 +/-0.02 Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481 rotational and lateral movement requirements (see sketches A, B, and C). 20 deg maximum Typical component cavity center line 0.5mm maximum B0 20 deg maximum component rotation 0.5mm maximum Sketch A (Side or Front Sectional View) Component Rotation A0 Sketch B (Top View) Typical component center line Sketch C (Top View) Component lateral movement SSOT-6 Reel Configuration: Figure 4.0 Component Rotation W1 Measured at Hub Dim A Max Dim A max Dim N See detail AA 7" Diameter Option B Min Dim C See detail AA W3 Dim D min 13" Diameter Option W2 max Measured at Hub DETAIL AA Dimensions are in inches and millimeters Tape Size 8mm Reel Option 7" Dia Dim A 7.00 177.8 13.00 330 Dim B 0.059 1.5 0.059 1.5 Dim C 512 +0.020/-0.008 13 +0.5/-0.2 512 +0.020/-0.008 13 +0.5/-0.2 Dim D 0.795 20.2 0.795 20.2 Dim N 2.165 55 4.00 100 Dim W1 0.331 +0.059/-0.000 8.4 +1.5/0 0.331 +0.059/-0.000 8.4 +1.5/0 Dim W2 0.567 14.4 0.567 14.4 Dim W3 (LSL-USL) 0.311 – 0.429 7.9 – 10.9 0.311 – 0.429 7.9 – 10.9 8mm 13" Dia July 1999, Rev. C SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued SuperSOT -6 (FS PKG Code 31, 33) 1:1 Scale 1:1 on letter size paper Dimensions shown below are in: inches [millimeters] Part Weight per unit (gram): 0.0158 1998 Fairchild Semiconductor Corporation September 1998, Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ DISCLAIMER ISOPLANAR™ MICROWIRE™ POP™ PowerTrench  QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™ FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. D