NM95MS18

NM95MS18 Plug 'n' Play Front End Device for ISA-Bus Systems July 1998 NM95MS18 Plug & Play Front-end device for ISA-Bus Systems (Supports Windows®-NT, UNIX® and legacy systems) General Description The NM95MS18 is an industry standard ISA Plug-n-Play controller that also supports Non-Plug-n-Play platforms like DOS, WIN3.1x, Windows-NT and Unix. In additon to being completely compliant to ISA PnP Specification (Ver 1.0a), NM95MS18 integrates a total of 4Kbit of onchip EEPROM for both PnP Resource data as well as non-PnP configuration data to provide a true single chip solution. NM95MS18 supports one logical device offering a flexible choice of DMA, Interrupt and I/O address decoding features within a single chip. NM95MS18 is implemented using Fairchild’s Advanced CMOS process and operates on a single power supply. s Supports Non-PnP platforms like WINDOWS-NT, UNIX, DOS/WIN3.1x — No configuration utilities needed s Supports Non-PnP "legacy" mode — Can be programmed to power-up in 31 settings s On-chip "Write-Protected" EEPROM for: — PnP Resource data (2Kbits) — 31 Power-on "legacy" configurations (2Kbits) s Two modes of operation: — DMA Mode — Extended Interrupt Mode (supports PC-97 requirements) s Configurable Interrupt types: — TTL O/P — Open Drain O/P s Supports Wire-AND I/O chipselects s Fully compatible with NM95MS16 s Available in 52-Pin PLCC Package Features s Fully compliant with industry standard ISA PnP specification (Ver. 1.0a) Block Diagram ISA BUS From Switches NPNP RSTDRV SW[0:4] Input Sense Logic Test Mode Logic SA[0:11] IORD IOWR AEN OSC PnP Cycle Detection Logic State Machine EEPROM Controller I/F IRQ Switch Logic IRQIN[0:1] IRQOUT[0:7] SD[0:7] Data Buffer Registers DMA Switch Logic DRQIN DACKOUT ISADRQ[0:1] ISADACK[0:1] SA[0:15] IORD IOWR AEN ADDRESS DECODER IOCS[0:2] DS500033-1 © 1998 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com NM95MS18 Plug 'n' Play Front End Device for ISA-Bus Systems Block Signal Description Signal SA[0:11] SA[12:15]† IORD* IOWR* AEN OSC RSTDRV SD[0:7] IRQIN0 IRQIN1† IRQOUT[0:5] IRQOUT[6:7] † DRQIN† ISADRQ[0:1] † ISADACK[0:1]* † DACKOUT* † IOCS[0:1]* IOCS[2]* † N_P 'N' P* Type I I I I I I I I/O I I O O I O I I O O I Address inputs from the ISA bus. Address inputs from the ISA bus. I/O Read strobe from the ISA bus. I/O Write strobe from the ISA bus. Description Address Enable Strobe from ISA bus. 14.31818 MHz clock source from ISA bus. Reset signal from ISA bus. ISA Data bus. Source Interrupt signal from onboard controller. Source Interrupt signal from onboard controller. Interrupt output signals from NM95MS18. Can be connected to any of ISA IRQ channels. Interrupt output signals from NM95MS18. Can be connected to any of ISA IRQ channels. Source DMA request signal from onboard controller to NM95MS18. DMA request output signals from NM95MS18. Can be connected to any of ISA DMA channels. DMA Acknowledge output signals from respective ISA DMA channels to which ISADRQ[0:1] are connected. DMA acknowledge signal from NM95MS18 to onboard controller. Programmable chipselects from NM95MS18 to onboard controller. Programmable chipselects from NM95MS18 to onboard controller. Input signal selecting either PNP mode or N_PNP mode of NM95MS18. This signal has a weak internal pull-up resistor defaulting to PnP mode and can be directly connected to ground . This signal is used in conjunction with SW[0:4] inputs. “1” - PNP mode. “0” N_PNP mode. Input signals to NM95MS18 selecting 1-out-of-31 Non-Plug-n-Play configurations. All these signals have a weak internal pull-up resistor and can be directly connected to ground. These signals are used in conjunction with N_PNP signal. SW[0:4] I * Signal name with a “*” indicates active low signal. † Multiplexed signals. Please refer Pinout Details. IRQOUT4 IRQOUT3 IRQOUT2 IRQOUT1 IRQOUT0 ISADRQ0 N_PNP* ISADRQ1 ISADACK0* ISADACK1* SW0 SW1 SA0 7 6 5 4 3 2 1 52 51 50 49 48 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IRQOUT5 IRQIN0 IRQIN1 GND DACKOUT* DRQIN NC VCC IOWR* IORD* IOCS0* IOCS1* RSTDRV 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SD7 SD6 SD5 SD4 SD3 SD2 SW4 SD1 SD0 OSC AEN SW3 SW2 SA1 SA2 SA3 SA4 GND SA5 NC SA6 SA7 SA8 SA9 SA10 SA11 DS500033-2 PLCC Pins 2 www.fairchildsemi.com NM95MS18 Plug 'n' Play Front End Device for ISA-Bus Systems Pinout Details for NM95MS18 (PLCC Package) Pin # Mode 1 2** (Note 3) 3** 4 5** 6 7 8 9 10 11 12 13** 14 15** 16** 17** 18 19 20 21 22 23 24 25 26 NC DRQIN DACKOUT* GND IRQIN1 IRQIN0 IRQOUT5 IRQOUT4 IRQOUT3 IRQOUT2 IRQOUT1 IRQOUT0 ISADRQ0 N_PnP ISADRQ1 ISADACK0* ISADACK1* SW0 SW1 SA0 SA1 SA2 SA3 SA4 GND SA5 Pin Name DMA NC SA15 IOCS2* GND SA14 IRQIN0 IRQOUT5 IRQOUT4 IRQOUT3 IRQOUT2 IRQOUT1 IRQOUT0 IRQOUT6 N_PnP IRQOUT7 SA12 SA13 SW0 SW1 SA0 SA1 SA2 SA3 SA4 GND SA5 Pin # Mode 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 NC SA6 SA7 SA8 SA9 SA10 SA11 SW2 SW3 AEN OSC SD0 SD1 SW4 SD2 SD3 SD4 SD5 SD6 SD7 RSTDRV IOCS1* IOCS0* IORD* IOWR* VCC Pin Name DMA NC SA6 SA7 SA8 SA9 SA10 SA11 SW2 SW3 AEN OSC SD0 SD1 SW4 SD2 SD3 SD4 SD5 SD6 SD7 RSTDRV IOCS1* IOCS0* IORD* IOWR* VCC Ext. Intr Ext. Intr ** Pins with multiplexed signals 3 www.fairchildsemi.com NM95MS18 Plug 'n' Play Front End Device for ISA-Bus Systems Absolute Maximum Ratings (Note 1) Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 seconds) ESD Rating –65°C to +150°C VCC + 1V to –0.3V +300°C 2000V min. Operating Conditions Ambient Operating Temperature NM95MS18 Positive Power Supply (VCC) 0°C to +70°C 4.5V to 5.5V Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook sepcifications. DC Electrical Characteristics Symbol ICCA ILI ILO VIL VIH VOL VOH Parameter Active Power Supply Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output HIGH Voltage Test Conditions fSCL = 100 kHz VIN = GND to VCC VOUT = GND to VCC Min Limits Typ (Note 2) TBD 0.2 Max 10.0 1.0 1.0 Units mA µA µA V V V V V -0.1 2.0 IOL = 24 mA (Note 4) IOL = 2.1 mA (Note 5) IOH = -3 mA (Note 4) IOH = -400 µA (Note 5) 2.4 2.4 0.8 VCC + 1.0 0.4 Capacitance TA = +25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O (Note 3) CIN (Note 3) COUT (Note 3) Test Conditions Input/Output Capacitance Input Capacitance Output Capacitance Min VI/O = 0V VIN = 0V VOUT = 0V Max 8 6 6 Units pF pF pF Note 2: Typical values are for TA = 25°C and nominal supply voltage (5V). Note 3: This parameter is periodically sampled and not 100% tested. Note 4: These values are for ISA signals like SD[0:7], IRQx, DRQx. Note 5: These values are for card signal like IOCS[0:2]*, DO(EEPROM) AC Electrical characteristics Symbol tAEN tAC tRVD tAH tRDH tWD tWDH tCSA tCSC tIDD Parameter AEN valid to command active Address valid to command active Active read to valid data Address, AEN hold from inactive command Read data hold from inactive read Write data valid before write active Write data hold after write inactive Chip selects valid from address valid Chip selects valid from command active Propagation delay for IRQ/DRQ/DACK Min 100 88 Max Unit ns ns 150 30 5 22 25 5 5 5 20 20 20 ns ns ns ns ns ns ns ns 4 www.fairchildsemi.com NM95MS18 Plug 'n' Play Front End Device for ISA-Bus Systems Timing Diagrams Timings for ISA Read/Write Cycle AEN tAEN tAH VALID ADDRESS SA[0:15] tAC tRVD tRDH IORD* IOWR* READ DATA SD[0:7] tWD WRITE DATA SD[0:7} tWDH VALID DS500033-3 Decode Delay for Chipselect Generation tCSA VALID ADDRESS SA[0:15] tCSA IOCS[0:1]* (addr decode only) tCSC tCSC IORD* IOWR* IOCS[0:1]* (Qualfied with CMD) DS500033-4 Propagation Delay for IRQ/DRQ/DACK tIDD IRQ in DRQ in ISADACK tIDD IRQ out DRQ out DACKOUT DS500033-5 INTRODUCTION NM95MS18 supports both Plug-n-Play platforms (PC with WINDOWS-95 and/or PnP BIOS) as well as Non-Plug-n-Play platforms (PC with WINDOWS-NT, Win3.x/DOS and Non-PnP BIOS). The choice of interface (PnP or Non-PnP) is selected by using a single pin (N_PnP*). Under PnP interface, NM95MS18 is fully compliant with ISA Plug-n-Play specification (Ver 1.0a) and is functionally compatible to its predecessor NM95MS16. Under Non-P 'n' P interface, NM95MS18 powers-up active with a prede- termined configuration eliminating any need for an external PnP configuration support. Five external inputs to NM95MS18 allows to choose the default power-up configuration from 31 different predetermined configurations. NM95MS18 integrates 2 kbits of on-board EEPROM to store all the 31 configuration information as well as an additional 2 kbits EEPROM area to store standard PnP resource information. Entire memory can be write protected. NM95MS18 also allows ISA interrupts to be shared. 5 www.fairchildsemi.com NM95MS18 Plug 'n' Play Front End Device for ISA-Bus Systems Functional Description As mentioned above, NM95MS18 can be configured for either Plug-n-Play environment or Non-Plug-n-Play environment. Under either interface, NM95MS18 provides a choice from 2 operating modes, viz, DMA Mode or Extended Interrupt Mode offering additional flexibility in selecting a suitable set of features for a particular application. Mode selection is made by setting appropriate bits in the "I/O DECODE QUALIFICATION" register in onboard EEPROM. Refer to "NM95MS18 User's Guide" for more detail. Each of these modes is explained below. SA[0:11] and IORD*/IOWR* or just by SA[0:11]. In addition IOCS1* signal can be internally Wire-ANDed with IOCS0* signal, to provide "Output Enable" signal for ISA bus data buffers. 2. Two local Interrupt request signals switchable to any six IRQ channels on the ISA Bus. Choice of actual ISA IRQ channels selected is user dependent. Also the type of the six IRQ outputs can be independently set to be either standard TTL type or Open-Drain type. Selecting Open-Drain type allows interrupts to be shared on the ISA bus. 3. One local DMA request signal switchable to any two DMA channels on the ISA Bus. Choice of actual ISA DMA channels selected is user dependent. Following figure shows a typical system block diagram of NM95MS18 used in DMA Mode. DMA Mode In the DMA Mode, NM95MS18 provides the following features: 1. Two programmable I/O chipselects (IOCS0*and IOCS1*) each of which can be set to be decoded off of ISA address DMA Mode DMA Mode ON Switch OFF NPNP* SW0 SW1 SW2 SW3 SW4 GND VCC RSTDRV OSC IORD* IOWR* IOCSO IOCS1 10K Extended Interrupt Mode (Supports PC-95/PC-97 Requirements) In Extended Interrupt Mode, NM95MS18 provides these features: 1. Three programmable I/O chipselects (IOCS0*, IOCS1* and IOCS2*) each of which can be set to be decoded off of ISA address SA[0:11] and and IORD*/IOWR* or by just ISA address bus only. In addition IOCS1* and IOCS2* signals can be internally Wire-ANDed with IOCS0* signal, to provide "Output Enable" signal for ISA bus data buffers. ISA Bus AEN SA[0:11] SD[0:7] IRQOUT[0:5] ISADRQ[0:1] ISADACK[0:1] NM95MS18 (DMA Mode) 10K IRQIN[0:1] DRQIN DACKOUT SOUND Controller DS500033-6 2. One on-board Interrupt request signals switchable to any eight IRQ channels on the ISA Bus. Choice of actual ISA IRQ channels selected is user dependent. Also the type of the eight IRQ outputs can be independently set to be either standard TTL type or Open-Drain type. Selecting OpenDrain type allows interrupts to be shared on the ISA bus. Following figure shows a typical system block diagram of NM95MS18 used in Extended Interrupt Mode. 6 www.fairchildsemi.com NM95MS18 Plug 'n' Play Front End Device for ISA-Bus Systems Extended Interrupt Mode (Supports PC-95/PC-97 Requirements) Extended Interrupt Mode ON Switch OFF NPNP* SW0 SW1 SW2 SW3 SW4 GND VCC RSTDRV OSC IORD* IOWR* IOCS0 IOCS1 IOCS1 10K Interface Options of NM95MS18 Plug-n-Play/Non-Plug-n-Play) 1) Plug-n-Play (PnP) Interface ("/N_PNP" = 1) In a Plug-n-Play environment, a PnP configuration manager (typically PnP-BIOS, Windows’95 OS or PnP utility) that resides on the PC would read the Plug-n-Play Resource data fileand allocate the requested resource (I/O Address space, IRQ etc). PnP configuration is actually a defined process of updating defined PnP Registers on a PnP controller in a defined manner. The entire protocol and Register summary is provided in the ISA PnP Specification (Ver 1.0a). NM95MS18 is designed to be completely compliant with the existing ISA PnP standard and hence provides seamless PnP support for an ISA adapter. All that is required is to prepare the Plug-n-Play Resource data for an applicatDuring power-up, NM95MS18 defaults to Plug-n-Play interface if it senses logic "high" at the "N_PNP*" pin. This pin has an internal weak pullup logic and hence can be left unconnected for PnP interface. Configuration #31 • • • • Configuration #3 Configuration #2 Configuration #1 ISA Bus AEN SA[0:15] SD[0:7] IRQOUT[0:5] NM95MS18 (Extended Interrupt Mode) ISDN Controller IRQIN0 DS500033-7 2) Non-Plug-n-Play (legacy) Interface ("/N_PNP" = 0) In a legacy interface NM95MS18 is designed to ignore the standard PnP configuration protocol and instead self-configure to a specific configuration. A specific configuration is selected by a set of switch inputs SW[0:4]. All possible combinations of these 5 inputs provide 31 configurations to choose from (the 32nd configuration is reserved for field programming. Refer section on "Software Write Configuration" for more detail). It is also possible to use fewer than five switch inputs (SW[0:3], SW[0:2], SW[0:1] or SW[0] to have fewer legacy configurations (15, 7, 3 or 1 respectively). All these five switch inputs have weak internal pull-up resistor allowing unused switch pins to be left unconnected when necessary. During power-up, NM95MS18 defaults to Legacy interface if it senses logic “low” at the “N_P 'n' P*” pin. Along with “N_P 'n' P*” pin, the state of “SW[0:4]” inputs are also sensed to determine the particular legacy configuration that needs to be selected. Each legacy configuration occupies 8 bytes (4 Words) of internal memory as shown in the following figure. Word IOCS0 (MSB) IOCS1 (MSB) IOCS2 (MSB) IRQIN1 IRQIN0 Bit[7:4] Bit[3:0] IOCS0 (LSB) IOCS1 (LSB) IOCS2 (LSB) IRQIN1 IRQIN0 TYPE TYPE Bit[7:6] Bit[5:4] 8 bytes/ configuration Bit[2:0] X Bit[3] DRQIN DS500033-8 7 www.fairchildsemi.com NM95MS18 Plug 'n' Play Front End Device for ISA-Bus Systems Interface Options of NM95MS18 (Plugn-Play/Non-Plug-n-Play) (Continued) Configuration #1 (first configuration) is stored at the bottom 8 bytes (higher address) of the memory and is selected when the SW[0:4] input reflects a “01111” combination. Following table describes all the configuration information with respect to SW[0:4] values and internal memory address. Configuration Number Configuration #1 Configuration #2 Configuration #3 Configuration #4 Configuration #5 Configuration #6 Configuration #7 Configuration #8 Configuration #9 Configuration #10 Configuration #11 Configuration #12 Configuration #13 Configuration #14 Configuration #15 Configuration #16 Configuration #17 Configuration #18 Configuration #19 Configuration #20 Configuration #21 Configuration #22 Configuration #23 Configuration #24 Configuration #25 Configuration #26 Configuration #27 Configuration #28 Configuration #29 Configuration #30 Configuration #31 Software Write /N_PnP Signal 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW[0:4] Combination 0-1-1-1-1 1-0-1-1-1 0-0-1-1-1 1-1-0-1-1 0-1-0-1-1 1-0-0-1-1 0-0-0-1-1 1-1-1-0-1 0-1-1-0-1 1-0-1-0-1 0-0-1-0-1 1-1-0-0-1 0-1-0-0-1 1-0-0-0-1 0-0-0-0-1 1-1-1-1-0 0-1-1-1-0 1-0-1-1-0 0-0-1-1-0 1-1-0-1-0 0-1-0-1-0 1-0-0-1-0 0-0-0-1-0 1-1-1-0-0 0-1-1-0-0 1-0-1-0-0 0-0-1-0-0 1-1-0-0-0 0-1-0-0-0 1-0-0-0-0 0-0-0-0-0 1-1-1-1-1 Memory Location (Word Address) 0xFC - 0xFF 0xF8 - 0xFB 0xF4 - 0xF7 0xF0 - 0xF3 0xEC - 0xEF 0xE8 - 0xEB 0xE4 - 0xE7 0xE0 - 0xE3 0xDC - 0xDF 0xD8 - 0xDB 0xD4 - 0xD7 0xD0 - 0xD3 0xCC - 0xCF 0xC8 - 0xCB 0xC4 - 0xC7 0xC0 - 0xC3 0xBC - 0xBF 0xB8 - 0xBB 0xB4 - 0xB7 0xB0 - 0xB3 0xAC - 0xAF 0xA8 - 0xAB 0xA4 - 0xA7 0xA0 - 0xA3 0x9C - 0x9F 0x98 - 0x9B 0x94 - 0x97 0x90 - 0x93 0x8C - 0x8F 0x88 - 0x8B 0x84 - 0x87 - Memory Location (Byte Address) 0x1F8 - 0x1FF 0x1F0 - 0x1F7 0x1E8 - 0x1EF 0x1E0 - 0x1E7 0x1D8 - 0x1DF 0x1D0 - 0x1D7 0x1C8 - 0x1CF 0x1C0 - 0x1C7 0x1B8 - 0x1BF 0x1B0 - 0x1B7 0x1A8 - 0x1AF 0x1A0 - 0x1A7 0x198 - 0x19F 0x190 - 0x197 0x188 - 0x18F 0x180 - 0x187 0x178 - 0x17F 0x170 - 0x177 0x168 - 0x16F 0x160 - 0x167 0x158 - 0x15F 0x150 - 0x157 0x148 - 0x14F 0x140 - 0x147 0x138 - 0x13F 0x130 - 0x137 0x128 - 0x12F 0x120 - 0x127 0x118 - 0x11F 0x110 - 0x117 0x108 - 0x10F - 8 www.fairchildsemi.com NM95MS18 Plug 'n' Play Front End Device for ISA-Bus Systems Internal EEPROM Memory of NM95MS18 PnP Memory (264 Bytes) 512 Bytes (4 K-Bits) Non-PnP Config Memory (248 Bytes) PnP Memory (392 Bytes) PnP Memory (456 Bytes) PnP Memory (512 Bytes) ••• Non-PnP Config Memory (120 Bytes) Using 15 Non-PnP Configurations Non-PnP Config Memory (56 Bytes) Using 31 Non-PnP Configurations Using 7 Non-PnP Configurations No Non-PnP Configurations DS500033-9 NM95MS18 has a total of 4Kbits (512 Bytes) onboard EEPROM. Of the 512 Bytes, a mimimum of 264 Bytes are allocated for storing Plug-n-Play Resource data and the remaining 248 Bytes can be used for storing up to 31 different default power-on NonPnP configurations (a.k.a. legacy configurations). As shown in the above figure, depending on the number of legacy configurations supported (can be 31 or 15 or 7 or 3 or 1 or 0), the space for storing Plug-n-Play Resource data can be extended to 512 bytes. PROGRAMMING OF ONCHIP EEPROM The entire 4Kbit internal EEPROM can be programmed through the ISA bus or through MICROWIRE interface (TEST Mode). Each method is explained below. PROGRAMMING THROUGH ISA BUS This method is suited for in-circuit programmin where NM95MS18 is assembled on the ISA board before programming. NM95MS18 is shipped with a “1” pattern at all its bit locations from factory. This means it is shipped with “Write-Protection” disabled. Depending whether the “Write-Protection” is enabled or not there are two procedures to program the onchip memory. Each of these two procedures are explained below. SOFTWARE WRITE CONFIGURATION Under Non-PnP mode when SW[0:4] inputs reflect a 1-1-1-1-1 pattern, NM95MS18 selects a configuration called “Software Write”. Primary use of this configuration is to allow field programming of the internal memory. Need for a field programming might arise if the predetermined 31 legacy configurations are exhausted and needs to be updated with a new set of 31 (or less) legacy configurations. Software-Write configuration overrides the general Write-Protection (refer Write-Protection section) offered by NM95MS18, temporarily. Under this “Software Write” configuration the NM95MS18 expects an “Extended LFSR” key which is nothing but the regular 32 byte writes of LFSR sequence (as defined in the PnP Specification) followed by a 33rd byte write where the value is “0x9C”. Once the 33rd write is detected, NM95MS18 will automatically transtition to the “CONFIG” state of PnP mode where programming of internal memory is enabled. In this configuration NM95MS18 selects ISA address “0x203” as the default Read_Data_Port, by default. PROGRAMMING WHEN "WRITE-PROTECTION" IS DISABLED Follow the procedure defined in ISA Plug-n-Play Specification (Ver. 1.0 a) to place NM95MS18 in "Config" mode of Plug-n-Play protocol. Once the device is is config state, programming of internal EEPROM is enabled. Programming is done by first setting the Address of the location, Data(16bit) to be programmed and then the "Go Ahead" bit to start the programming. A bit in the Status register provides the status of the operation. A programming utility is also available from Fairchild. Following table summarizes all the registers involved during programming. WRITE PROTECTION NM95MS18 offers “Write-Protection” for the entire 4Kbits of internal memory. Protection is enabled by setting bit[15] of the “I/ O DECODE QUALIFICATION” register to “0”. Setting this bit to “1” disables write-protection. Under “Software Write configuration” this bit is overridden and write-protection is disabled. 9 www.fairchildsemi.com NM95MS18 Plug 'n' Play Front End Device for ISA-Bus Systems Internal EEPROM Memory of NM95MS18 (Continued) PROGRAMMING INTERFACE Programming EEPROM Register Name Status and Command Register Register 0xF0 Definition Bit[1:0} OP Code bits 10 - Read operation 01 - Write operation 11 - Erase operation Bit [2] - GA (Go Ahead bits) If set to 1, the programming will continue Bit [7:3] - Reserved, should be 0 Address register [A0 - A7] Data Byte [MSB] Data Byte [LSB] Bit [0]: STATUS/BUSY bit during programming, ‘0’ is BUSY, ‘1’ is done Address Register Data Register Data Register STATUS Register 0xF1 0xF2 0xF3 0x05 PROGRAMMING WHEN “WRITE-PROTECTION” IS ENABLED In this case, programming is enabled when N_PNP* pin is “0” and the SW[0:4] inputs are “11111”. Programming procedure is same as programming when Write-Protection is disabled with the exception of LFSR sequence. In this case 33-Byte Extended-LSFR should be used instead of 32-Byte LFSR. PROGRAMMING THROUGH MICROWIRE INTERFACE (TEST MODE) This method is suited when NM95MS18 is pre-programmed before board assembly. This method involves using special TEST mode of NM95MS18. Once the device is in TEST mode, the entire internal memory can be programmed like a standard Micro-wire EEPROM. The protocol to place the device in “test-mode” makes use of the following three signals, viz. RESETDRV, IRQIN0 and SW0. The timing diagram is shown below. RESTDRV 5V 500 ns 100 ns 100 ns Start of standard Micro-wire access 500 ns 5V IRQIN0 12V 100 ns 100 ns SW0 300 ns DS500033-10 Note: All timings shown here are minimum values. 10 www.fairchildsemi.com NM95MS18 Plug 'n' Play Front End Device for ISA-Bus Systems Internal EEPROM Memory of NM95MS18 (Continued) Details of timing information for Microwire protocol can be obtained from Fairchild’s Microwire EEPROM Datasheets. Please refer NM93C66 datasheet. This datasheet can be downloaded from Fairchild’s home page on World-Wide-Web. (http:// www.fairchildsemi.com) resource allocation probabilities and also allows presence of multiple cards of the same type. Each IRQOUTx signal can be individually set for either Interrupt type and this is done by setting appropriate bits in EEPROM register. Refer the USER’S GUIDE for more detail. Wire-ANDing of I/O Chipselects The IOCS1* and IOCS2* signals can be internally Wire-ANDed with IOCS0* signal on NM95MS18. When this feature is enabled, IOCS0* signal can also act as “Output Enable” signal for ISA bus data buffers eliminating extra glue logic on the board. Setting appropriate bits in EEPROM register enables this feature. Refer the USER’S GUIDE for more detail. Following diagram illustrates this feature. SHARING OF INTERRUPTS Interrupt output (IRQOUTx) signals from NM95MS18 can be configured as either standard TTL type or Open-Drain type. Interrupt outputs configured as Open-Drain type can share an interrupt on the ISA bus. Sharing of interrupt increases ISA bus SA[0:15] Base Address for IOCS0 IORD*/IOWR IOCS0*
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,  WIRE-ANDing of I/O Chipselects Base Address for IOCS1 Base Address for IOCS2 IOCS1* Wire-ANDed with IOCS0* IOCS2* Wire-ANDed with IOCS0* DS500033-11 IOCS1* IOCS2* Note 1: This illustratory waveform assumes that both IOCS1* and IOCS2* are set to be Wire-ANDed with IOCS0*. They can also be set individually. Note 2: In this waveform, IOCSx* are set to be decoded off of address and IORD*/IOWR. Note 3: Refer “I/O DECODE QUALIFICATION REGISTER” description for more information. 11 www.fairchildsemi.com NM95MS18 Plug 'n' Play Front End Device for ISA-Bus Systems Physical Dimensions inches (millimeters) unless otherwise noted 0.750 - 0.756 [19.05 - 19.20] 0.013–0.021 TYP [0.33–0.53] 1 52 47 46 0.026–0.032 TYP [0.66–0.81] 0.690–0.730 TYP [17.53–18.54] 45°X0.045 [1.14] Pin 1 IDENT 7 8 45° X 0.045 [1.14] 20 21 0.050 TYP [1.27] 0.600 [15.24] TYP 33 34 0.020 MIN TYP [0.51] 0.090–0.130 TYP [2.29–3.30] 0.165–0.180 TYP [4.19–4.57] 0.785 - 0.795 [19.94 - 20.19] 52 Lead Molded Plastic Leaded Chip Carrier Package Number V52A Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Français Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383 Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 12 www.fairchildsemi.com