RFD12N06RLE

RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Data Sheet January 2002 17A, 60V, 0.071 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging JEDEC TO-251AA DRAIN (FLANGE) SOURCE DRAIN GATE GATE SOURCE Features JEDEC TO-252AA DRAIN (FLANGE) • Ultra Low On-Resistance - rDS(ON) = 0.063Ω, VGS = 10V - rDS(ON) = 0.071Ω, VGS = 5V • Simulation Models - Temperature Compensated PSPICE® and SABER© Electrical Models - Spice and SABER© Thermal Impedance Models - www.fairchildsemi.com • Peak Current vs Pulse Width Curve • UIS Rating Curve • Switching Time vs RGS Curves RFD12N06RLE RFD12N06RLESM SOURCE DRAIN GATE JEDEC TO-220AB DRAIN (FLANGE) RFP12N06RLE Ordering Information PART NUMBER PACKAGE TO-251AA TO-252AA TO-220AB BRAND 12N6LE 12N6LE 12N06RLE RFD12N06RLE Symbol D RFD12N06RLESM RFP12N06RLE G NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-252AA variant in tape and reel, i.e. RFD12N06RLESM9A. S Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE 60 60 ±16 17 18 8 8 Figure 4 Figures 6, 17, 18 49 0.327 -55 to 175 300 260 UNITS V V V A A A A Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TC= 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 135oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 135oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTE: 1. TJ = 25oC to 150oC. W W/oC oC oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ©2002 Fairchild Semiconductor Corporation RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Rev. B RFD12N06RLE, RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Electrical Specifications PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVDSS IDSS IGSS VGS(TH) rDS(ON) ID = 250µA, VGS = 0V (Figure 12) ID = 250µA, VGS = 0V , T C = -40oC (Figure 12) Zero Gate Voltage Drain Current VDS = 55V, VGS = 0V VDS = 50V, VGS = 0V, TC = 150oC Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250µA (Figure 11) ID = 18A, VGS = 10V (Figures 9, 10) ID = 8A, VGS = 5V (Figure 9) ID = 8A, VGS = 4.5V (Figure 9) THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RθJC RθJA TO-251AA, TO-252AA 3.06 100 oC/W oC/W TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 60 55 - - 1 250 ±100 V V µA µA nA VGS = ±16V 1 - 0.052 0.060 0.064 3 0.063 0.071 0.075 V Ω Ω Ω SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 30V, ID = 8A, Ig(REF) = 1.0mA (Figures 14, 19, 20) VDD = 30V, ID = 18A VGS = 10V, RGS = 24Ω (Figures 16, 21, 22) VDD = 30V, ID = 8A VGS = 4.5V, RGS = 22Ω (Figures 15, 21, 22) 13 89 22 37 153 89 ns ns ns ns ns ns SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain “Miller” Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance 485 130 28 pF pF pF 12 6.8 0.54 1.7 3 15 8.2 0.65 nC nC nC nC nC 5.3 34 41 50 59 136 ns ns ns ns ns ns Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage SYMBOL VSD trr QRR ISD = 8A ISD = 4A Reverse Recovery Time Reverse Recovered Charge ISD = 8A, dISD/dt = 100A/µs ISD = 8A, dISD/dt = 100A/µs TEST CONDITIONS MIN TYP MAX 1.25 1.0 70 165 UNITS V V ns nC ©2002 Fairchild Semiconductor Corporation RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Rev. B RFD12N06RLE, RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 15 VGS = 10V 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) 20 10 VGS = 4.5V 5 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 1 THERMAL IMPEDANCE ZθJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101 SINGLE PULSE 0.01 10-5 10-4 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 200 IDM, PEAK CURRENT (A) 100 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150 VGS = 5V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101 FIGURE 4. PEAK CURRENT CAPABILITY ©2002 Fairchild Semiconductor Corporation RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Rev. B RFD12N06RLE, RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Typical Performance Curves 100 (Continued) 60 IAS, AVALANCHE CURRENT (A) If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] ID, DRAIN CURRENT (A) 100µs 10 10 STARTING TJ = 25oC 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TC = 25oC 1ms 10ms STARTING TJ = 150oC 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 1 0.01 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms) NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 5. FORWARD BIAS SAFE OPERATING AREA 20 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A) 15 20 VGS = 10V VGS = 5V ID, DRAIN CURRENT (A) 15 VGS = 3.5V 10 VGS = 4V 10 TJ = 25oC 5 TJ = 175oC 0 1.0 2.0 3.0 4.0 5.0 TJ = -55oC 5 TC = 25oC 0 0 VGS = 3V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 4 VGS, GATE TO SOURCE VOLTAGE (V) 1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS 80 NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE (mΩ) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC 2.5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID = 17A 70 ID = 12A ID = 7A 60 2.0 1.5 50 1.0 VGS = 10V, ID = 18A 0.5 -80 -40 0 40 80 120 160 200 40 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE ©2002 Fairchild Semiconductor Corporation RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Rev. B RFD12N06RLE, RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Typical Performance Curves 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.0 (Continued) 1.2 ID = 250µA 1.1 0.8 1.0 0.6 0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 0.9 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 10 VGS , GATE TO SOURCE VOLTAGE (V) 2000 1000 C, CAPACITANCE (pF) CISS = CGS + CGD VDD = 30V 8 6 100 COSS ≅ CDS + CGD 4 2 VGS = 0V, f = 1MHz 10 0.1 WAVEFORMS IN DESCENDING ORDER: ID = 17A ID = 12A ID = 7A 0 3 6 9 Qg, GATE CHARGE (nC) 12 15 CRSS = CGD 60 0 1.0 10 VDS , DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 150 VGS = 4.5V, VDD = 30V, ID = 8A SWITCHING TIME (ns) SWITCHING TIME (ns) 120 tr 90 100 VGS = 10V, VDD = 30V, ID = 18A 80 60 tf tr 60 tf 40 td(OFF) 30 td(ON) 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE (Ω) td(OFF) 20 0 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE (Ω) 50 td(ON) FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE ©2002 Fairchild Semiconductor Corporation RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Rev. B RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01Ω 0 tAV FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS VDS RL VDD VDS VGS = 10V VGS + Qg(TOT) Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V DUT Ig(REF) FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS VDS tON td(ON) RL VDS + tOFF td(OFF) tr tf 90% 90% VGS VDD DUT 0 10% 90% 10% RGS VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM ©2002 Fairchild Semiconductor Corporation RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Rev. B RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE PSPICE Electrical Model .SUBCKT HUF76409D 2 1 3 ; CA 12 8 6.30e-10 CB 15 14 6.30e-10 CIN 6 8 4.60e-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD 10 rev 23 August 1999 LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + EBREAK MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 17 18 DBODY DRAIN 2 RSLC1 51 ESLC 50 RSLC2 5 51 ESG 6 8 + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6 IT 8 17 1 LDRAIN 2 5 1.00e-9 LGATE 1 9 3.73e-9 LSOURCE 3 7 3.43e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1.88e-2 RGATE 9 20 3.76 RLDRAIN 2 5 10 RLGATE 1 9 37.3 RLSOURCE 3 7 34.3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 2.40e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD - - VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*43),3))} .MODEL DBODYMOD D (IS = 3.84e-13 RS = 1.56e-2 TRS1 = -1.0e-3 TRS2 = 7.0e-6 CJO = 6.4e-10 TT = 5.10e-8 XTI =4.35 M = 0.52) .MODEL DBREAKMOD D (RS = 3.70e- 1TRS1 = 9.10e- 4TRS2 = -1e-6) .MODEL DPLCAPMOD D (CJO = 3.70e-1 0IS = 1e-3 0N = 10 M = 0.79) .MODEL MMEDMOD NMOS (VTO = 2.08 KP = 3.2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.76) .MODEL MSTROMOD NMOS (VTO = 2.40 KP = 28 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.80 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 37.6 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.13e- 3TC2 = -3.00e-7) .MODEL RDRAINMOD RES (TC1 = 9.80e-3 TC2 = 2.85e-5) .MODEL RSLCMOD RES (TC1 = 5.00e-3 TC2 = 5.05e-6) .MODEL RSOURCEMOD RES (TC1 = 1.5e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -1.48e-3 TC2 = -8.30e-6) .MODEL RVTEMPMOD RES (TC1 = -1.68e- 3TC2 = 8e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -5 VOFF= -2.8) VON = -2.8 VOFF= -5) VON = -0.5 VOFF= 0.5) VON = 0.5 VOFF= -0.5) NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2002 Fairchild Semiconductor Corporation + - EBREAK 11 7 17 18 66.55 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RDRAIN 21 16 - VBAT + 8 22 RVTHRES RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Rev. B RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE SABER Electrical Model REV 23 August 1999 template huf76409d n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 3.84e-13, cjo = 6.40e-10, tt = 5.10e-8, xti = 4.35, m = 0.52) d..model dbreakmod = () d..model dplcapmod = (cjo = 3.70e-10, is = 1e-30, m = 0.79) m..model mmedmod = (type=_n, vto = 2.08, kp = 3.2, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.40, kp = 28, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.80, kp = 0.08, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5, voff = -2.8) DPLCAP sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.8, voff = -5) 10 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.5) c.ca n12 n8 = 6.30e-10 c.cb n15 n14 = 6.30e-10 c.cin n6 n8 = 4.60e-10 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.00e-9 l.lgate n1 n9 = 3.73e-9 l.lsource n3 n7 = 3.43e-9 GATE 1 RLGATE CIN LGATE RSLC2 ISCL LDRAIN 5 RLDRAIN RDBREAK 72 DBREAK 11 MWEAK MMED MSTRO 8 EBREAK + 17 18 71 RDBODY DRAIN 2 RSLC1 51 ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 DBODY m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.13e-3, tc2 = -3.00e-7 res.rdbody n71 n5 = 1.56e-2, tc1 = -1.0e-3, tc2 = 7.00e-6 res.rdbreak n72 n5 = 3.70e-1, tc1 = 9.10e-4, tc2 = -1e-6 res.rdrain n50 n16 = 1.88e-2, tc1 = 9.80e-3, tc2 = 2.85e-5 res.rgate n9 n20 = 3.76 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 37.3 res.rlsource n3 n7 = 34.3 res.rslc1 n5 n51= 1e-6, tc1 = 5.00e-3, tc2 = 5.05e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.40e-2, tc1 = 1.5e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.68e-3, tc2 = 8.00e-7 res.rvthres n22 n8 = 1, tc1 = -1.48e-3, tc2 = -8.30e-6 spe.ebreak n11 n7 n17 n18 = 66.55 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/43))** 3)) } } S1A 12 13 8 S1B CA 13 + EGS 6 8 S2A 14 13 S2B - LSOURCE 7 RLSOURCE SOURCE 3 RSOURCE RBREAK 17 18 RVTEMP CB + EDS 5 8 19 14 IT 15 VBAT + - - 8 RVTHRES 22 ©2002 Fairchild Semiconductor Corporation RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Rev. B RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE SPICE Thermal Model REV 10 September 1999 HUF76409T CTHERM1 th 6 9.50e-4 CTHERM2 6 5 2.40e-3 CTHERM3 5 4 3.90e-3 CTHERM4 4 3 4.10e-3 CTHERM5 3 2 5.60e-3 CTHERM6 2 tl 4.00e-2 RTHERM1 th 6 2.00e-2 RTHERM2 6 5 1.10e-1 RTHERM3 5 4 2.75e-1 RTHERM4 4 3 5.53e-1 RTHERM5 3 2 7.25e-1 RTHERM6 2 tl 7.56e-1 RTHERM1 CTHERM1 th JUNCTION 6 RTHERM2 CTHERM2 5 RTHERM3 CTHERM3 SABER Thermal Model SABER thermal model HUF76409T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 9.50e-4 ctherm.ctherm2 6 5 = 2.40e-3 ctherm.ctherm3 5 4 = 3.90e-3 ctherm.ctherm4 4 3 = 4.10e-3 ctherm.ctherm5 3 2 = 5.60e-3 ctherm.ctherm6 2 tl = 4.00e-2 rtherm.rtherm1 th 6 = 2.00e-2 rtherm.rtherm2 6 5 = 1.10e-1 rtherm.rtherm3 5 4 = 2.75e-1 rtherm.rtherm4 4 3 = 5.53e-1 rtherm.rtherm5 3 2 = 7.25e-1 rtherm.rtherm6 2 tl = 7.56e-1 } 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl CASE ©2002 Fairchild Semiconductor Corporation RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT ™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ DISCLAIMER FAST ® FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench ® QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER ® SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET ® VCX™ STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4