RFD3055SM

RFD3055, RFD3055SM, RFP3055 D ata Sheet January 2002 12A, 60V, 0.150 Ohm, N-Channel Power MOSFETs These are N-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA49082. Features • 12A, 60V • rDS(ON) = 0.150Ω • Temperature Compensating PSPICE® Model • Peak Current vs Pulse Width Curve • UIS Rating Curve • 175oC Operating Temperature • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol D Ordering Information PART NUMBER RFD3055 RFD3055SM RFP3055 PACKAGE TO-251AA TO-252AA TO-220AB BRAND FD3055 FD3055 FP3055 G S NOTE: When ordering, use the entire part number. Add the suffix 9A, to obtain the TO-252AA variant in tape and reel, i.e. RFD3055SM9A. Packaging JEDEC TO-251AA JEDEC TO-252AA SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (FLANGE) GATE SOURCE JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) ©2002 Fairchild Semiconductor Corporation RFD3055, RFD3055SM, RFP3055 Rev. B RFD3055, RFD3055SM, RFP3055 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD3055, RFD3055SM, RFP3055 60 60 ±20 12 Refer to Peak Current Curve Refer to UIS Curve 53 0.357 -55 to 175 300 260 UNITS V V V A A W W/oC oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20KΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Single Pulse Avalanche Rating (Figures 14, 15) . . . . . . . . . . . . . . . . . . . . . . . . . . IAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) CISS COSS CRSS RθJC RθJA TO-251 and TO-252 TO-220 VGS = 0 to 20V VGS = 0 to 10V VGS = 0 to 2V VDD = 48V,ID = 12A, RL = 4Ω, Ig(REF) = 0.24mA (Figure 13) TEST CONDITIONS ID = 250µA, VGS = 0V (Figure 11) VGS = VDS , ID = 250µA (Figure 10) VDS = Rated BVDSS , VGS = 0V TC = 125oC, VDS = 0.8 x Rated BVDSS VGS = ±20V ID = 12A, VGS = 10V (Figure 9) (Note 2) VDD = 30V, ID = 12A RL = 2.5Ω , VGS = +10V RG = 10Ω (Figure 13) MIN 60 2 TYP 7 21 16 10 19 10 0.6 300 100 30 MAX 4 1 25 100 0.150 40 40 23 12 0.8 2.8 100 62.5 UNITS V V µA µA nA Ω ns ns ns ns ns ns nC nC nC pF pF pF oC/W oC/W oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time NOTES: 2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5). SYMBOL VSD trr ISD = 12A ISD = 12A, dISD /dt = 100A/µs TEST CONDITIONS MIN TYP MAX 1.5 100 UNITS V ns ©2002 Fairchild Semiconductor Corporation RFD3055, RFD3055SM, RFP3055 Rev. B RFD3055, RFD3055SM, RFP3055 Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150 175 Unless Otherwise Specified 14 12 ID , DRAIN CURRENT (A) 10 8 6 4 2 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE ZθJC, NORMALIZED TRANSIENT 1 THERMAL IMPEDANCE 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 100 101 PDM t1 , RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 50 IDM , PEAK CURRENT CAPABILITY (A) 200 TC = 25oC ID , DRAIN CURRENT (A) FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS: 175 – T C I = I 25 * --------------------150 10 100µs 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms DC 100 VGS = 20V 1 VGS = 10V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-3 10-2 10-1 100 101 102 t, PULSE WIDTH (ms) 103 104 0.1 TC = 25oC TJ = MAX RATED SINGLE PULSE 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 100 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY ©2002 Fairchild Semiconductor Corporation RFD3055, RFD3055SM, RFP3055 Rev. B RFD3055, RFD3055SM, RFP3055 Typical Performance Curves 50 IAS , AVALANCHE CURRENT (A) Unless Otherwise Specified (Continued) 24 VGS = 10V ID , DRAIN CURRENT (A) STARTING TJ = 25oC 18 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 8V VGS = 7V 10 STARTING TJ = 150oC 12 VGS = 6V 6 VGS = 5V VGS = 4.5V 0 If R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IF R ≠ 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 0.01 0.1 tAV, TIME IN AVALANCHE (ms) 1 1 0.001 0 1.5 3.0 4.5 6.0 VDS , DRAIN TO SOURCE VOLTAGE (V) 7.5 FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS 24 ID , ON STATE DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON RESISTANCE VDS = 15V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 2.5 -55oC 25oC 2.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 12A 18 175oC 12 1.5 1.0 6 0.5 0 0 2 4 6 8 10 VGS , GATE TO SOURCE VOLTAGE (V) 0 -80 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160 200 FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE NORMALIZED GATE THRESHOLD VOLTAGE 2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS , ID = 250µA 2.0 ID = 250µA 1.5 1.5 1.0 1.0 0.5 0.5 0 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 200 0 -80 -40 0 80 120 160 40 TJ , JUNCTION TEMPERATURE (oC) 200 FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs TEMPERATURE FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs TEMPERATURE ©2002 Fairchild Semiconductor Corporation RFD3055, RFD3055SM, RFP3055 Rev. B RFD3055, RFD3055SM, RFP3055 Typical Performance Curves 600 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 400 CISS Unless Otherwise Specified (Continued) 60 VDD = BVDSS 45 VDD = BVDSS 7.5 10 VGS, GATE TO SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 30 0.75 BVDSS 0.75 BVDSS 0.50 BVDSS 0.50 BVDSS 0.25 BVDSS 0.25 BVDSS RL = 5Ω IG(REF) = 0.24mA VGS = 10V 5.0 200 COSS CRSS 15 2.5 0 0 5 10 15 20 VDS , DRAIN TO SOURCE VOLTAGE (V) 25 0 20 0 IG(REF) IG(ACT) t, TIME (µs) 80 IG(REF) IG(ACT) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + - 0V IAS 0.01Ω 0 tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VDS 90% tOFF td(OFF) tf 90% + RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS ©2002 Fairchild Semiconductor Corporation RFD3055, RFD3055SM, RFP3055 Rev. B RFD3055, RFD3055SM, RFP3055 Test Circuits and Waveforms (Continued) VDS RL VDD VDS VGS = 20V VGS + Qg(TOT) Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Ig(REF) 0 VGS = 10V DUT Ig(REF) FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS ©2002 Fairchild Semiconductor Corporation RFD3055, RFD3055SM, RFP3055 Rev. B RFD3055, RFD3055SM, RFP3055 PSPICE Electrical Model .SUBCKT RFP3055 2 1 3 ; CA 12 8 0.540e-9 CB 15 14 0.540e-9 CIN 6 8 0.300e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 67.9 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.61e-9 LSOURCE 3 7 4.61e-9 GATE 1 LGATE RGATE 9 rev 10/26/93 DPLCAP 10 5 LDRAIN RSCL1 DRAIN 2 RSCL2 DBREAK + 51 5 ESCL 51 50 RDRAIN 16 11 + 17 EBREAK 18 MOS2 DBODY ESG 6 8 + VTO + 21 EVTO + 18 8 RIN 6 CIN MOS1 8 RSOURCE 7 LSOURCE 3 SOURCE MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 1e-4 RGATE 9 20 7.23 RIN 6 8 1e9 RSCL1 5 51 RSLVCMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 108e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.5 12 S1A 13 8 S1B CA EGS 13 + 6 8 14 13 S2A 15 S2B CB + EDS 5 8 14 IT RBREAK 17 18 RVTO 19 VBAT + ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/30,6.5))} .MODEL DBDMOD D (IS=4.33e-14 RS=2.78e-2 TRS1=1.10e-3 TRS2=5.19e-6 CJO=3.94e-10 TT=7.63e-8) .MODEL DBKMOD D (RS=0.676 TRS1=1.94e-3 TRS2=-1.09e-6) .MODEL DPLCAPMOD D (CJO=0.238e-9 IS=1e-30 N=10) .MODEL MOSMOD NMOS (VTO=4.078 KP=12 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=1.06e-3 TC2=-1.92e-6) .MODEL RDSMOD RES (TC1=5.03e-3 TC2=1.53e-5) .MODEL RSLVCMOD RES (TC1=2.2e-3 TC2=-5e-6) .MODEL RVTOMOD RES (TC1=-5.02e-3 TC2=-9.16e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.5 VOFF=-3.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-6.5) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.50 VOFF=2.50) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2.50 VOFF=-2.50) .ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFet Featuring Global Temperature Options; authored by William J. Hepp and C. Frank Wheatley. ©2002 Fairchild Semiconductor Corporation RFD3055, RFD3055SM, RFP3055 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT ™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ DISCLAIMER FAST ® FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench ® QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER ® SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET ® VCX™ STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4