RFD4N06LSM

RFD4N06L, RFD4N06LSM D ata Sheet January 2002 4A, 60V, 0.600 Ohm, Logic Level, N-Channel Power MOSFETs The RFD4N06L, RFD4N06LSM are N-Channel enhancement mode silicon gate power field effect transistors specifically designed for use with logic level (5 volt) driving sources in applications such as programmable controllers, automotive switching, and solenoid drivers. This performance is accomplished through a special gate oxide design which provides full rated conduction at gate biases in the 3-5 volt range, thereby facilitating true on-off power control from logic circuit supply voltages. Formerly developmental type TA09520. Features • 4A, 60V • rDS(ON) = 0.600Ω • Design Optimized for 5 Volt Gate Drive • Can be Driven Directly From Q-MOS, N-MOS, or TTL Circuits • SOA is Power Dissipation Limited • 175oC Rated Junction Temperature • Logic Level Gate • High Input Impedance • Related Literature Ordering Information PART NUMBER RFD4N06L RFD4N06LSM PACKAGE TO-251AA TO-252AA BRAND RFD4N06L RFD4N06LSM - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol D NOTE: When ordering, use the entire part number. G S Packaging JEDEC TO-251AA SOURCE DRAIN GATE GATE SOURCE JEDEC TO-252AA DRAIN (FLANGE) DRAIN (FLANGE) ©2002 Fairchild Semiconductor Corporation RFD4N06L, RFD4N06LSM Rev. B RFD4N06L, RFD4N06LSM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD4N06L RFD4N06LSM 60 60 ±10 4 10 30 0.20 -55 to 175 300 260 UNITS V V V A A W W/oC oC oC oC Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derated above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 1mA, VGS = 0V VGS = VDS, ID = 250µA TC = 25oC, VDS = 50V, VGS = 0V TC = 125oC, VDS = 50V, VGS = 0V VGS = ±10V, VDS = 0V ID = 1A, VGS = 5V ID = 2A, VGS = 5V ID = 4A, VGS = 7.5V MIN 60 1 VGS = 0-10V VGS = 0-5V VGS = 0-1V VDD = 48V, ID = 2A, RL = 24Ω TYP MAX 2.5 1 50 ±100 0.8 2.0 4.0 0.600 4.5 20 130 40 160 8 5 1 5 UNITS V V µA µA nA V V V Ω V ns ns ns ns nC nC nC oC/W Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Voltage (Note 2) IGSS VDS(ON) Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate Charge at 5V Threshold Gate Charge Thermal Resistance Junction to Case rDS(ON) ID = 1A, VGS = 5V VDD = 30V, ID = 1A, RGS = 6.25Ω, VGS = 5V V(plateau) VDS = 15V, ID = 4A td(ON) tr td(OFF) tf Qg(TOT) Qg(5) Qg(TH) RθJC Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage (Note 2) Reverse Recovery Time NOTES: 2. Pulsed: pulse duration = 300µs max, duty cycle = 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. SYMBOL VSD trr ISD = 1A ISD = 2A, dISD/dt = 100A/µs TEST CONDITIONS MIN TYP 150 MAX 1.4 UNITS V ns ©2002 Fairchild Semiconductor Corporation RFD4N06L, RFD4N06LSM Rev. B RFD4N06L, RFD4N06LSM Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 Unless Otherwise Specified 5 ID, DRAIN CURRENT (A) 4 3 2 1 0 25 50 75 100 125 150 50 TC, CASE TEMPERATURE (oC) 75 100 125 TC, CASE TEMPERATURE (oC) 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 10 TJ = MAX RATED TC = 25oC ID, DRAIN CURRENT (A) 12 10 8 6 4 2 0 PULSE DURATION = 80µs TC = 25oC VGS = 10V VGS = 7.5V ID, DRAIN CURRENT (A) 1.0 OPERATION IN THIS AREA LIMITED BY rDS(ON) VGS = 5V 4.5V 4V 3.5V 3V 2.5V 2V 7 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 0 1 2 3 4 5 6 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. SATURATION CHARACTERISTICS IDS(ON), DRAIN TO SOURCE CURRENT (A) 8 7 6 5 TC = -40oC 4 3 2 1 0 TC = -40oC 1 2 3 4 5 6 VGS, GATE TO SOURCE VOLTAGE (V) TC = 125oC TC = 125oC TC = 25oC VDS = 10V PULSE DURATION = 80µs DUTY CYCLE ≤ 2% 1.6 VGS = 5V 1.4 PULSE DURATION = 80µs rDS(ON), DRAIN TO SOURCE ON RESISTANCE(Ω) 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 ID, DRAIN CURRENT (A) 8 10 TC = 25oC TC = -40oC TC = 125oC FIGURE 5. TRANSFER CHARACTERISTICS FIGURE 6. DRAIN TO SOURCE ON RESISTANCE vs DRAIN CURRENT ©2002 Fairchild Semiconductor Corporation RFD4N06L, RFD4N06LSM Rev. B RFD4N06L, RFD4N06LSM Typical Performance Curves 2 VGS = 5V, ID = 2A Unless Otherwise Specified (Continued) 2 VGS = VDS, ID = 250µA NORMALIZED DRAIN TO SOURCE ON RESISTANCE 1 THRESHOLD VOLTAGE NORMALIZED GATE 1.5 1.5 1 0.5 0.5 0 -50 0 50 100 150 200 0 -50 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) FIGURE 7. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 400 FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 60 VDS, DRAIN TO SOURCE VOLTAGE (V) 10 VGS, GATE TO SOURCE VOLTAGE (V) RL = 4Ω IG(REF) = 0.5mA VGS = 5V GATE SOURCE VOLTAGE VDD = BVDSS VDD = BVDSS C, CAPACITANCE (pF) 300 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 8 45 6 200 CISS 30 4 15 0.75BVDSS 0.50BVDSS 0.25BVDSS DRAIN SOURCE VOLTAGE 0 0 20 IG(REF) IG(ACT) t, TIME (µs) 80 IG(REF) IG(ACT) 100 COSS CRSS 2 0 0 10 20 30 40 50 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 9. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 10. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms tON td(ON) tr RL VDS + tOFF td(OFF) tf 90% 90% RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 11. SWITCHING TIME TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS ©2002 Fairchild Semiconductor Corporation RFD4N06L, RFD4N06LSM Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT ™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ DISCLAIMER FAST ® FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench ® QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER ® SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET ® VCX™ STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4