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RMLA3565C-TB

RMLA3565C-TB

  • 厂商:

    FAIRCHILD(仙童半导体)

  • 封装:

  • 描述:

    RMLA3565C-TB - Wideband Low Noise MMIC Amplifier - Fairchild Semiconductor

  • 数据手册
  • 价格&库存
RMLA3565C-TB 数据手册
RMLA3565C May 2004 RMLA3565C Wideband Low Noise MMIC Amplifier General Description The Fairchild Semiconductor’s RMLA3565C is a single bias wideband low noise MMIC amplifier designed for the 3.5– 6.5 GHz frequency range. The MMIC requires no external matching circuits or external gate bias supply. This device uses our advanced 0.25µm PHEMT process to provide low noise, high linearity, and low current. Features • 20dB Gain typical • 1.2dB Noise Figure Typical 5.0–6.5GHz • 4.0V Single Positive Bias • Small Outline Metal Base Quad Plastic Package • Internal 50Ω Matching Device Absolute Ratings Symbol Vdd PIN (CW) Idd Tcase Tstorage Tsolder Rjc Parameter Positive Drain DC Voltage RF Input Power (from 50Ω source) Drain Current Case Operating Temperature Storage Temperature Range Soldering Temperature Thermal Resistance (Channel to Case) Ratings 6.5 0 130 -30 to 85 -40 to 110 220 8 Units V dBm mA °C °C °C °C/W Electrical Characteristics (50Ω System, Vdd = 4V, T = +25°C) Parameter Frequency Range Gain (Small Signal)1, 2 Gain Variation vs Temp Noise Figure2 3.5–5 GHz 5–6.5 GHz Power Out, P-1dB OIP3 @ 5.5 GHz, 0 dBm per tone Pout Idd Vdd Input/Output Return Loss Notes: 1. Pin = -20, Vd = 4.0V, Frequency 3.5–6.5Ghz 2. Data de-embedded from fixture loss. ©2004 Fairchild Semiconductor Corporation RMLA3565C Rev. C Min 3.5 17.0 Typ 20 0.013 1.5 1.2 13 25.5 80 4.0 10.0 Max 6.5 Units GHz dB dB/C° dB dB dBm dBm mA V dB 2.2 1.6 8.0 3.0 90 6.0 RMLA3565C Application Information CAUTION: THIS IS AN ESD SENSITIVE DEVICE The following briefly describes a procedure for evaluating the high efficiency PHEMT amplifier packaged in a surface mount package. It may be noted that the chip is a fully monolithic single ended two stage amplifier for 3.5 to 6.5 GHz applications. Figure 1 shows the functional block diagram of the packaged product. Test Fixture Figure 2 shows the outline and pin-out descriptions for the packaged device. A typical test fixture schematic showing external bias components is shown in Figure 3. Figure 4 shows typical layout of an evaluation board corresponding to the schematic diagram. Typical performance of the test fixture is shown in the performance data section. The following should be noted: (1) Package pin designations are shown in Figure 2. (2) Vd is the drain voltage (positive) applied at the pins of the package. (3) Vdd is the positive supply voltage at the evaluation board terminal. GROUND Pin# 5 MMIC CHIP GROUND Pin# 1, 3, 4, 6, 9, 10, 11, 13 GROUND Pin# 7 RF IN Pin# 8 RF OUT Pin# 2 Vd Pin# 12 Figure 1. Functional Block Diagram Top View 0.200 SQ. 6 5 4 Bottom View 4 5 6 7 3 2 0.015 3 7 8 9 2 1 0.030 8 9 1 0.020 0.011 10 11 12 12 11 10 0.041 Plastic Lid 0.010 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Description GND RF Out GND GND GND GND GND RF In GND GND GND Vd GND (Package Base) 0.075 MAX 0.230 0.246 0.282 Side Section Dimensions in inches Figure 2. Package Outline Dimensions ©2004 Fairchild Semiconductor Corporation RMLA3565C Rev. C RMLA3565C RF In J1 RMLA3565C-58 RF Out J2 GND P2 C1 (OPT) C2 (OPT) Vdd P1 C3 Figure 3. Schematic for a Typical Test Evaluation Board (RMLA3565C-TB) Pin 5 must be grounded U1 RF In J1 Fairchild RF Out J2 C1 & C2 (OPT) C3 GROUND (GND) P2 Vdd P1 Figure 4. Layout and Assembly of Test Evaluation Board (RMLA3565C-TB) Test Procedure for the evaluation board (RMLA3565C-TB) The following sequence of procedure must be followed to properly test the power amplifier: Step 1: Turn off RF input power. Step 2: Use GND terminal of the evaluation board to connect DC supply grounds and Pin 5. Step 3: Apply drain supply voltage of +4.0V to evaluation board terminal Vdd. Step 4: After the bias condition is established, RF input signal may now be applied. Step 5: Follow turn-off sequence of: (i) Turn off RF input power. (ii) Turn down and off Vdd. ©2004 Fairchild Semiconductor Corporation RMLA3565C Rev. C RMLA3565C Parts List For Test Evaluation Board (RMLA3565C-TB) Part C1 C2 C3 U1 P1, P2 J1, J2 Board Value 330 pF 1000 pF 4.75 µF RMLA3565C Terminals SMA Connectors RO4003 (Rogers) Size (EIA) .04” x .02” .04” x .02” .14” x .11” .28” x .28” x .07” Vendor(s) AVX, Murata, Novacap AVX, Murata, Novacap Sprague, ATC, AVX, Murata Fairchild Samtec E.F. Johnson Fairchild 1.99 x 1.50 x .032 Typical Characteristics RMLA3565CS-Parameters vs. Frequency 4V 80mA 20 15 10 Pout (dBm) Sij (dB) 0 -10 -20 -30 S11 (dB) S21 (dB) S22 (dB) 20 RMLA3565C Pout vs Pin 4V 80mA 10 5 0 -5 -10 -30 3.5 GHz 4.5 GHz 5.5 GHz 6.5 GHz 0 1 2 3 4 5 6 7 Frequency (GHz) 8 9 10 -25 -20 -15 Pin (dBm) -10 -5 0 2 1.8 RMLA3565C Noise Figure vs. Frequency 4V 80mA 27 26 25 24 OIP3 (dBm) 23 22 21 20 19 18 RMLA3565C OIP3 vs Single Tone Pout Tone Sep = 1MHz F = 5.5GHz 4V 80mA 1.6 NF (dB) 1.4 1.2 1 0.8 3.5 4 4.5 5 Frequency (GHz) 5.5 6 17 -4 -2 0 2 4 6 1TPout (dBm) 8 10 12 86 85 84 83 Idd (mA) 82 81 80 79 78 77 -25 -20 RMLA3565C Idd vs. Pin Vdd = 4V -15 Pin (dBm) -10 -5 ©2004 Fairchild Semiconductor Corporation RMLA3565C Rev. C TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FAST ActiveArray™ FASTr™ Bottomless™ FPS™ CoolFET™ FRFET™ CROSSVOLT™ GlobalOptoisolator™ DOME™ GTO™ EcoSPARK™ HiSeC™ E2CMOS™ I2C™ EnSigna™ i-Lo™ FACT™ ImpliedDisconnect™ FACT Quiet Series™ ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC Across the board. Around the world.™ OPTOPLANAR™ PACMAN™ The Power Franchise POP™ Programmable Active Droop™ Power247™ PowerSaver™ PowerTrench QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ µSerDes™ SILENT SWITCHER SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic TINYOPTO™ TruTranslation™ UHC™ UltraFET VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I11
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