RMPA2451-TB

RMPA2451 April 2004 RMPA2451 2.4–2.5 GHz GaAs MMIC Power Amplifier General Description Fairchild Semiconductor’s RMPA2451 is a partially matched monolithic power amplifier in a surface mount package for use in wireless applications in the 2.4 to 2.5 GHz ISM frequency band. The amplifier may be biased for linear, class AB or class F for high efficiency applications. External matching components are required to optimize the RF performance. The MMIC chip design utilizes our 0.25µm power Pseudomorphic High Electron Mobility (PHEMT) process. Features • 38% power added efficiency • 29dBm typical output power • Small package outline: 0.28" x 0.28" x 0.07" • Low power mode: 0 dBm Device Absolute Ratings Symbol Vd1, Vd2 Vg1, Vg2 Vd–Vg PIN Id1 Id2 Ig TC TCASE TSTG RJC Parameter Positive Drain DC Voltage Negative Gate DC Voltage Simultaneous Drain to Gate Voltage RF Input Power (from 50Ω source) Drain Current, First Stage Drain Current, Second Stage Gate Current Channel Temperature Operating Case Temperature Storage Temperature Range Thermal Resistance (Channel to Case) Min 0 -5 Max +8 0 +10 +10 75 525 5 175 85 125 33 Units V V V dBm mA mA mA °C °C °C °C/W -40 -40 ©2004 Fairchild Semiconductor Corporation RMPA2451 Rev. B RMPA2451 Electrical Characteristics1 Parameter Frequency Range Gain1 Output Power, P1dB1 Power Added Efficiency 3rd order Intermod. Product2 Drain Current (Id1 + Id2) Gate Current (Ig1 + Ig2) Input Return Loss (50W) Low Power Mode, Pout3 Min 2400 28.5 27 Typ 33 29 38 -35 430 2:1 0 Max 2500 Units MHz dB dBm % dBc mA mA dB dBm -27 5 Notes: 1. Production Testing includes Gain, Output Power at1-dB gain compression (P1dB) and Input Return Loss at Vd1 = Vd2 = +5.0; Vg1, Vg2 = -0.5V (nominal), adjust Vg1 and Vg2 to get Idq1 = 60mA, Idq2 = 340mA and at F = 2.45GHz, at 25°C. 2. Two tone 3rd order Output Intermodulation products (IM3) are measured with total output power level of 25dBm (tone spacing is 1MHz). 3. Vg1, Vg2 tied together. Vd = 5V until Idq total = 45 mA, Pin = -10dBm. Other Parameters are guaranteed by Design Validation Testing (DVT) ©2004 Fairchild Semiconductor Corporation RMPA2451 Rev. B RMPA2451 Application Information CAUTION: THIS IS AN ESD SENSITIVE DEVICE. The following describes the procedure for evaluating the RMPA2451, a partially-matched PHEMT monolithic power amplifier which has been designed for wireless applications in the 2.4 - 2.5 GHz ISM band, in a surface mount package. The package outline, along with the pin designations, is provided as Figure 1. The functional block diagram of the packaged product is provided as Figure 2. It should be noted that the RMPA2451 requires the use of external passive components to form the DC bias and RF output matching circuits. The schematic for a recommended DC bias / RF matching circuit is shown in Figure 3, along with a list of the appropriate components. Figure 4 illustrates the layout of an evaluation board based on this schematic (RMPA2451-TB). Figures 5 and 6 illustrate typical device performance. This data for various operating parameters was obtained across the design bandwidth over a range of temperatures. Figure 5 shows the variation in Gain and P1dB with temperature and operating frequency. Figure 6 shows the 3rd-order intermodulation product measured at different total output power levels. Top View 0.200 SQ. 6 5 4 Bottom View 4 5 6 7 3 2 0.015 3 7 8 9 2 1 0.030 8 9 1 0.020 0.011 10 11 12 12 11 10 0.041 Plastic Lid 0.008 0.015 0.282 Pin 1 2 3 4 5 6 7 8 9 10 11 12 Base Description Vd2 + RF Out Vd2 + RF Out Vd2 + RF Out GND Vd1 GND GND RF IN GND Vg1 Vg2 GND GND 0.075 MAX Side Section Dimensions in inches Figure 1. Package Information ©2004 Fairchild Semiconductor Corporation RMPA2451 Rev. B RMPA2451 Pin #5 Vd1 Pins #4, #6, #7, #9, #12 Ground MMIC CHIP Pin #8 RF INPUT Pins #1, #2, #3 RF OUTPUT & Vd2 GROUND (Back of the Chip) Pin #10 Vg1 Pin #11 Vg2 Figure 2. Functional Block Diagram Test Procedure for the Evaluation Board (RMPA2451-TB) It is important that the following points be noted prior to testing; Pin designations are as shown in Figure 2 and 4. • Vgg1 and Vgg2 are the negative Gate bias voltages applied at the pins of the evaluation test board. • Vdd1 and Vdd2 are the positive Drain bias voltages applied at the pins of the evaluation test board. • Vg1 and Vg2 are the negative Gate bias voltages applied at the pins of the package. • Vd1 and Vd2 are the positive Drain bias voltages applied at the pins of the package. CAUTION: LOSS OF GATE VOLTAGES (VG1, VG2) WHILE DRAIN VOLTAGES (VD1, VD2) ARE PRESENT MAY DAMAGE THE AMPLIFIER. The following sequence of procedures must be followed to properly test the amplifier: Step 1: Turn the RF power OFF. Step 2: Use the GND terminals of the evaluation board for the ground of the DC supplies. Step 3: Apply a nominal voltage of approximately - 3.0V to both Vgg1 and Vgg2 terminals. Step 4: Apply a nominal voltage of +5.0V to the Vdd terminals. Adjust Vgg2 to provide a second stage quiescent Drain current, Idd2, of 340 mA. Adjust Vgg1 to give a first stage quiescent Drain current, Id1 of 60mA. Step 5: Apply an RF signal within the ISM frequency range (2.4 - 2.5 GHz) at an initial input power level of -10 dBm. Step 6: To perform intermodulation product measurements, a second RF signal generator with a frequency difference of 1 MHz is required, along with an appropriate power combiner. The test configuration should allow this additional generator to provide the same input power level as the first generator into the device. Intermodulation readings may then be made at the required total output power levels. Step 7: To operate at lower quiescent Drain currents, increase the magnitudes of Vgg1 and Vgg2 as required, alternatively to operate at higher quiescent Drain currents, the magnitudes of Vgg1 and Vgg2 should be decreased accordingly. Step 8: When turning the amplifier OFF, the power-up sequence should be reversed. ©2004 Fairchild Semiconductor Corporation RMPA2451 Rev. B RMPA2451 V dd1 C2 C1 C3 RF INPUT L2 RMPA2451 PPYYWWX C3 RF OUTPUT L1 C4 V dd2 Vgg1 C2 C1 C1 C2 V gg2 C1 C2 Figure 3. Schematic of a Recommended DC Bias/RF Matching Circuit C3 L2 C1 + 654 C2 C3 C4 V dd1 RF INPUT 7 8 9 R 2 53 M 451PA 3 2 1 RF OUTPUT 10 1112 + + C1 C2 C1 + L1 C1 C2 C2 Vgg1 Vgg2 GND Vdd2 Parts Lists for Test Evaluation Board Part C1 C2 C3 C4 L1 L2 Value 1000pF 2.2µF 1.0pF 2.0pF 10.0nH 1.8nH Quantity 4 4 2 1 1 1 Supplier Murata Sprague Murata Murata Coilcraft Coilcraft Part Number GRM36X 595D225X0016T2T GRM36COG1R0B050 GRM36COG2R0B050 0805HT10NTKBC 0805HT1N8TKBC Figure 4. Layout of Evaluation Board (RMPA2451-TB) ©2004 Fairchild Semiconductor Corporation RMPA2451 Rev. B RMPA2451 Typical Characteristics Variation In Gain & P1dB With Frequency Over Temperature (Vdd = +5.0 V, Iddq = 60 + 340mA @ 25°C) 37.0 2.50GHz 2.45GHz 2.40GHz Gain (dB) 35.0 33.0 31.0 P1dB (dBm) 29.0 2.50GHz 2.45GHz 2.40GHz 27.0 25.0 -50 -30 -10 10 30 50 70 90 TEMPERATURE (°C) NB: Gain measured at Pin = -10dBm Figure 5. Typical Gain and P1dB Performance Across Bandwidth Over Temperature Variation In IM3 with Frequency & Temperature for Different Total Output Power Levels (Vdd = +5.0 V, Iddq = 60 + 340mA @ 25°C) -25.0 -27.0 3rd ORDER INTERMOD. PRODUCT (dBc) -29.0 2.50GHz -31.0 2.40GHz 2.45GHz PTOT = 25dBm -33.0 -35.0 2.50GHz -37.0 2.40GHz 2.45GHz -39.0 PTOT = 23dBm -41.0 -43.0 -50 -30 -10 10 30 50 70 90 TEMPERATURE (°C) Figure 6. Typical Third-Order Intermodulation Product Variation Over Temperature ©2004 Fairchild Semiconductor Corporation RMPA2451 Rev. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I10