SCAN182541A

SCAN182541A Non-Inverting Line Driver with 25Ω Series Resistor Outputs January 1993 Revised August 2000 SCAN182541A Non-Inverting Line Driver with 25Ω Series Resistor Outputs General Description The SCAN182541A is a high performance BiCMOS line driver featuring separate data inputs organized into dual 9bit bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary-Scan architecture with the incorporation of the defined Boundary-Scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK). Features s IEEE 1149.1 (JTAG) Compliant s High performance BiCMOS technology s 25Ω series resistor outputs eliminate need for external terminating resistors s Dual output enable signals per byte s 3-STATE outputs for bus-oriented applications s 25 mil pitch SSOP (Shrink Small Outline Package) s Includes CLAMP, IDCODE and HIGHZ instructions s Additional instructions SAMPLE-IN, SAMPLE-OUT and EXTEST-OUT s Power up 3-STATE for hot insert s Member of Fairchild’s SCAN Products Ordering Code: Order Number SCAN182541ASSC Package Number MS56A Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names AI(0–8) BI(0–8) AOE1, AOE2 BOE1, BOE2 AO(0–8) BO(0–8) Description Input Pins, A Side Input Pins, B Side 3-STATE Output Enable Input Pins, A Side 3-STATE Output Enable Input Pins, B Side Output Pins, A Side Output Pins, B Side © 2000 Fairchild Semiconductor Corporation DS011543 www.fairchildsemi.com SCAN182541A Truth Tables Inputs †AOE1 L H X L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Inputs AI(0–8) H X X L AO(0–8) H Z Z L †BOE1 L H X L †BOE2 L X H L BI(0–8) H X X L BO(0–8) H Z Z L †AOE2 L X H L Z = High Impedance † = Inactive-to-active transition must occur to enable outputs upon power-up. Block Diagrams Byte A Tap Controller Byte B Note: BSR stands for Boundary Scan Register. www.fairchildsemi.com 2 SCAN182541A Description of BOUNDARY-SCAN Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 The INSTRUCTION register is an 8-bit register which captures the default value of 10000001 (SAMPLE/PRELOAD) during the CAPTURE-IR instruction command. The benefit of capturing SAMPLE/PRELOAD as the default instruction during CAPTURE-IR is that the user is no longer required to shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of: CAPTURE-IR→EXIT1-IR→ UPDATE-IR will update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions. Instruction Register Scan Chain Definition MSB→LSB Instruction Code 00000000 10000001 Instruction EXTEST SAMPLE/PRELOAD CLAMP HIGH-Z SAMPLE-IN SAMPLE-OUT EXTEST-OUT IDCODE BYPASS BYPASS SCAN182541A Product IDCODE (32-Bit Code per IEEE 1149.1) Version Entity Part Number 0000 MSB Manufacture Required b r y ID 1149.1 1 LSB 10000010 00000011 01000001 01000010 00100010 10101010 11111111 All Others 111111 000000100 00000001111 1 Scan Cell TYPE1 Scan Cell TYPE2 3 www.fairchildsemi.com SCAN182541A Description of BOUNDARY-SCAN Circuitry (Continued) BOUNDARY-SCAN Register Scan Chain Definition (42 Bits in Length) www.fairchildsemi.com 4 SCAN182541A Description of BOUNDARY-SCAN Circuitry (Continued) Input BOUNDARY-SCAN Register Scan Chain Definition (22 Bits in Length) When SAMPLE-IN is Active 5 www.fairchildsemi.com SCAN182541A Description of BOUNDARY-SCAN Circuitry (Continued) Output BOUNDARY-SCAN Register Scan Chain Definition (20 Bits in Length) When SAMPLE-OUT and EXTEXT Out are Active www.fairchildsemi.com 6 SCAN182541A Description of BOUNDARY-SCAN Circuitry Bit No. 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pin Name AOE1 AOE2 AOE BOE1 BOE2 BOE AI0 AI1 AI2 AI3 AI4 AI5 AI6 AI7 AI8 BI0 BI1 BI2 BI3 BI4 BI5 BI6 BI7 BI8 AO0 AO1 AO2 AO3 AO4 AO5 AO6 AO7 AO8 BO0 BO1 BO2 BO3 BO4 BO5 BO6 BO7 BO8 55 53 52 50 49 47 46 44 43 42 41 39 38 36 35 33 32 30 2 4 5 7 8 10 11 13 14 15 16 18 19 21 22 24 25 27 26 31 Pin No. 3 54 (Continued) BOUNDARY-SCAN Register Definition Index Pin Type Input Input Internal Input Input Internal Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Scan Cell Type TYPE1 TYPE1 TYPE2 TYPE1 TYPE1 TYPE2 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 B–out A–out B–in A–in Control Signals 7 www.fairchildsemi.com SCAN182541A Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) EDS (HBM) Min. Twice the Rated IOL (mA) −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −0.5V to +5.5V −0.5V to VCC Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate Data Input Enable Input −40°C to +85°C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns −500 mA 10V 2000V Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Min Min Min VOL IIH Output LOW Voltage Input HIGH Current All Others Max TMS, TDI IBVI IBVIT IIL Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current All Others Max TMS, TDI VID Input Leakage Test Max 0.0 4.75 Max Max Max Max 5 5 7 100 −5 −5 −385 Min Max 2.5 2.0 0.8 5 VCC Min 2.0 0.8 −1.2 Typ Max Units V V V V V V µA µA µA µA µA µA µA µA V Conditions Recognized HIGH Signal Recognized LOW Signal IIN = −18 mA IOH = −3 mA IOH = −32 mA IOL = 15 mA VIN = 2.7V (Note 3) VIN = VCC VIN = VCC VIN = 7.0V VIN = 5.5V VIN = 0.5V (Note 3) VIN = 0.0V VIN = 0.0V IID = 1.9 µA All Other Pins Grounded IIH + IOZH IIL + LOZL IOZH IOZL IOS ICEX IZZ Output Leakage Current Output Leakage Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Max Max Max Max Max Max 0.0 −100 50 −50 50 −50 −275 50 100 µA µA µA µA mA µA µA VOUT = 2.7V VOUT = 0.5V VOUT = 2.7V VOUT = 0.5V VOUT = 0.0V VOUT = VCC VOUT = 5.5V All Others Grounded www.fairchildsemi.com 8 SCAN182541A DC Electrical Characteristics Symbol ICCH Parameter Power Supply Current (Continued) VCC Max Max Min Typ Max 250 1.0 65 65.8 250 1.0 2.9 3 0.2 Units µA mA mA mA µA mA mA mA mA/ MHz Conditions VOUT = VCC; TDI, TMS = VCC VOUT = VCC; TDI, TMS = GND VOUT = LOW; TDI, TMS = VCC VOUT = LOW; TDI, TMS = GND TDI, TMS = VCC TDI, TMS = GND VIN = VCC − 2.1V VIN = VCC − 2.1V Outputs Open One Bit Toggling, 50% Duty Cycle ICCL Power Supply Current Max Max ICCZ Power Supply Current Max Max ICCT Additional ICC/Input All Other Inputs TDI, TMS Inputs Max Max Max ICCD Dynamic ICC No Load Note 3: Guaranteed not tested. AC Electrical Characteristics Normal Operation: VCC Symbol Parameter (V) (Note 4) tPLH tPHL tPLZ tPHZ tPZL tPZH tPLH tPHL tPLZ tPHZ tPZL tPZH tPLH tPHL tPLH tPHL tPLH tPHL tPLZ tPHZ tPLZ tPHZ tPLZ tPHZ tPZL tPZH tPZL tPZH tPZL tPZH Propagation Delay TCK to TDO Disable Time TCK to TDO Enable Time TCK to TDO Propagation Delay TCK to Data Out during Update-DR State Propagation Delay TCK to Data Out during Update-IR State Propagation Delay TCK to Data Out during Test Logic Reset State Disable Time TCK to Data Out during Update-DR State Disable Time TCK to Data Out during Update-IR State Disable Time TCK to Data Out during Test Logic Reset State Enable Time TCK to Data Out during Update-DR State Enable Time TCK to Data Out during Update-IR State Enable Time TCK to Data Out during Test Logic Reset State 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Enable Time 5.0 Propagation Delay Data to Q Disable Time 5.0 5.0 Min 1.0 1.9 2.0 1.9 2.4 1.6 3.2 4.5 2.5 3.7 4.9 3.1 3.7 4.9 4.2 5.3 5.0 6.2 3.7 4.3 3.7 4.3 4.7 5.5 5.5 4.0 5.8 4.3 6.6 4.9 TA = −40°C to +85°C CL = 50 pF Typ 3.4 4.1 5.2 5.6 6.1 5.1 6.0 7.6 5.8 7.4 8.6 6.7 6.7 8.3 7.9 9.2 9.4 10.9 7.9 8.7 8.5 9.4 10.1 10.9 9.8 7.9 10.9 9.0 12.5 10.5 Max 5.2 6.5 8.7 9.2 9.6 8.5 9.4 11.3 9.9 11.8 12.9 10.7 10.3 12.4 12.2 13.8 14.6 16.4 13.0 13.7 14.2 14.8 16.6 17.3 14.7 12.5 16.5 14.4 19.1 16.9 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units Note 4: Voltage Range 5.0V ± 0.5V 9 www.fairchildsemi.com SCAN182541A AC Operating Requirements Scan Test Operation: VCC Symbol Parameter (V) (Note 5) tS tH tS tH tS Setup Time Data to TCK (Note 6) Hold Time Data to TCK (Note 6) Setup Time, H or L AOEn, BOEn to TCK (Note 7) Hold Time, H or L TCK to AOEn, BOEn (Note 7) Setup Time, H or L Internal AOEn, BOEn, to TCK (Note 8) tH Hold Time, H or L TCK to Internal AOEn, BOEn (Note 8) tS tH tS tH tW fMAX tPU tDN Setup Time, H or L TMS to TCK Hold Time, H or L TCK to TMS Setup Time, H or L TDI to TCK Hold Time, H or L TCK to TDI Pulse Width TCK L Maximum TCK Clock Frequency Wait Time, Power Up to TCK Power Down Delay 5.0 5.0 0.0 H 5.0 5.0 5.0 5.0 5.0 7.5 1.8 5.0 2.0 10.0 10.8 50 100 100 ns ns ns ns ns MHz ns ms 5.0 1.8 ns 5.0 2.7 ns 5.0 5.0 5.0 5.0 TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum 2.2 1.8 3.7 1.8 ns ns ns ns Units Note 5: Voltage Range 5.0V ± 0.5V Note 6: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35. Note 7: Timing pertains to BSR 38 and 41 or BSR 37 and 40. Note 8: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK. Capacitance Symbol CIN COUT Input Capacitance Output Capacitance (Note 9) Parameter Typ 5.8 13.8 Units pF pF Conditions, T A = 25°C VCC = 0.0V VCC = 5.0V Note 9: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.fairchildsemi.com 10 SCAN182541A Non-Inverting Line Driver with 25Ω Series Resistor Outputs Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com