SFP9620

Advanced Power MOSFET FEATURES Avalanche Rugged Technology Rugged Gate Oxide Technology Lower Input Capacitance Improved Gate Charge Extended Safe Operating Area Lower Leakage Current : -10 µA (Max.) @ VDS = -200V Low RDS(ON) : 1.111 Ω (Typ.) 1 2 3 SFP9620 BVDSS = -200 V RDS(on) = 1.5 Ω ID = -3.5 A TO-220 1.Gate 2. Drain 3. Source Absolute Maximum Ratings Symbol VDSS ID IDM VGS EAS IAR EAR dv/dt PD TJ , TSTG TL Characteristic Drain-to-Source Voltage Continuous Drain Current (TC=25 C) Continuous Drain Current (TC=100 C) Drain Current-Pulsed Gate-to-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Total Power Dissipation (TC=25 C) Linear Derating Factor Operating Junction and Storage Temperature Range Maximum Lead Temp. for Soldering Purposes, 1/8 “ from case for 5-seconds o o o Value -200 -3.5 -2.2 1 O Units V A A V mJ A mJ V/ns W W/ C o -14 + 30 _ 327 -3.5 3.8 -5.0 38 0.3 - 55 to +150 O 1 O 1 O 3 O 2 o C 300 Thermal Resistance Symbol RθJC RθCS RθJA Characteristic Junction-to-Case Case-to-Sink Junction-to-Ambient Typ. -0.5 -Max. 3.29 -62.5 o Units C/W Rev. B ©1999 Fairchild Semiconductor Corporation SFP9620 Symbol BVDSS ∆BV/∆TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd Characteristic Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coeff. Gate Threshold Voltage Gate-Source Leakage , Forward Gate-Source Leakage , Reverse Drain-to-Source Leakage Current Static Drain-Source On-State Resistance Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain( “ Miller “ ) Charge Min. Typ. Max. Units -200 --2.0 ------------------0.18 ------2.3 415 70 26 12 22 33 15 15 3.3 7.5 ---4.0 -100 100 -10 -100 1.5 -540 105 40 35 55 75 40 19 --nC ns pF µA Ω Ω V V nA P-CHANNEL POWER MOSFET Electrical Characteristics (TC=25oC unless otherwise specified) Test Condition VGS=0V,ID=-250µA See Fig 7 VDS=-5V,ID=-250µA VGS=-30V VGS=30V VDS=-200V VDS=-160V,TC=125 C VGS=-10V,ID=-1.8A VDS=-40V,ID=-1.8A 4 O 4 O o o V/ C ID=-250µA VGS=0V,VDS=-25V,f =1MHz See Fig 5 VDD=-100V,ID=-3.5A, RG=18Ω See Fig 13 45 OO VDS=-160V,VGS=-10V, ID=-3.5A See Fig 6 & Fig 12 45 OO Source-Drain Diode Ratings and Characteristics Symbol IS ISM VSD trr Qrr Characteristic Continuous Source Current Pulsed-Source Current Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge 1 O Min. Typ. Max. Units --------125 0.59 -3.5 -14 -5.0 --A V ns µC Test Condition Integral reverse pn-diode in the MOSFET TJ=25 C,IS=-3.5A,VGS=0V TJ=25 C,IF=-3.5A diF/dt=100A/µs 4 O o o O 4 Notes ; 1 Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature O 2 O L=40mH, I AS=-3.5A, V DD=-50V, R G=27Ω*, Starting T J =25oC 3 < _ < O ISD < -3.5A, di/dt _ 300A/µs, VDD_BVDSS , Starting T J =25oC _ 4 O Pulse Test : Pulse Width = 250 µs, Duty Cycle < 2% 5 Essentially Independent of Operating Temperature O P-CHANNEL POWER MOSFET Fig 1. Output Characteristics 1 10 V GS SFP9620 Fig 2. Transfer Characteristics [A] -ID , Drain Current 101 -ID , Drain Current [A] Top : - 15 V - 10 V - 8.0 V - 7.0 V - 6.0 V - 5.5 V - 5.0 V Bottom : - 4.5 V 0 10 100 150 oC 25 oC @ Notes : 1. V = 0 V GS 2. V = -40 V DS - 55 oC 3. 250 µs Pulse Test 10-1 @ Notes : 1. 250 µs Pulse Test 2. T = 25 oC C 100 1 10 10-1 10-1 2 4 6 8 10 -VDS , Drain-Source Voltage [V] -VGS , Gate-Source Voltage [V] RDS(on) , [ ] Ω Drain-Source On-Resistance Fig 3. On-Resistance vs. Drain Current 5 [A] Fig 4. Source-Drain Diode Forward Voltage 101 4 3 V = -10 V GS -IDR , Reverse Drain Current 100 150 oC 25 oC @ Notes : 1. V = 0 V GS 2. 250 µs Pulse Test 2 1 VGS = -20 V 0 0 2 4 6 8 10 12 14 @ Note : T = 25 oC J 10-1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -ID , Drain Current [A] -VSD , Source-Drain Voltage [V] Fig 5. Capacitance vs. Drain-Source Voltage Ciss= Cgs+ C ( Cds= shorted ) gd Coss= Cds+ C gd Fig 6. Gate Charge vs. Gate-Source Voltage [V] 800 [pF] Crss= Cgd 600 C iss 400 C oss @ Notes : 1. V = 0 V GS 2. f = 1 MHz -VGS , Gate-Source Voltage 10 VDS = -40 V VDS = -100 V VDS = -160 V Capacitance 5 200 C rss @ Notes : I =-3.5 A D 0 0 3 6 9 12 15 0 100 1 10 -VDS , Drain-Source Voltage [V] QG , Total Gate Charge [nC] SFP9620 Drain-Source Breakdown Voltage P-CHANNEL POWER MOSFET Fig 8. On-Resistance vs. Temperature Drain-Source On-Resistance 3.0 Fig 7. Breakdown Voltage vs. Temperature 1.2 -BV , (Normalized) DSS RDS(on) , (Normalized) 2.5 1.1 2.0 1.0 1.5 1.0 @ Notes : 1. V = -10 V GS 2. I = -1.8 A D -50 -25 0 25 50 75 100 125 150 175 0.9 @ Notes : 1. V = 0 V GS 2. I = -250 µA D -50 -25 0 25 50 75 100 o 0.5 0.8 -75 125 150 175 0.0 -75 TJ , Junction Temperature [ C] TJ , Junction Temperature [oC] [A] Fig 9. Max. Safe Operating Area Operation in This Area is Limited by R DS(on) 101 0.1 ms 1 ms 10 ms 100 @ Notes : 1. T = 25 oC C 2. T = 150 oC J 3. Single Pulse 10-1 100 101 102 DC Fig 10. Max. Drain Current vs. Case Temperature 4 -ID , Drain Current -ID , Drain Current [A] 3 2 1 0 25 50 75 100 125 150 -VDS , Drain-Source Voltage [V] Tc , Case Temperature [oC] Fig 11. Thermal Response Thermal Response D=0.5 10 0 0.2 0.1 0.05 10- 1 0.02 0.01 single pulse @ Notes : 1. Zθ J C (t)=3.29 o C/W Max. 2. Duty Factor, D=t1 /t 2 3. TJ M -T C =P D M *Z θ J C (t) P. DM t1. t2. Z θJC (t) , 10- 5 10- 4 10 - 3 10 - 2 10 - 1 100 10 1 t 1 , S quare Wave Pulse Duration [sec] P-CHANNEL POWER MOSFET Fig 12. Gate Charge Test Circuit & Waveform SFP9620 “ Current Regulator ” 50KΩ 12V 200nF 300nF Same Type as DUT VGS Qg -10V VDS VGS DUT -3mA Qgs Qgd R1 Current Sampling (IG) Resistor R2 Current Sampling (ID) Resistor Charge Fig 13. Resistive Switching Test Circuit & Waveforms RL Vout Vin RG DUT -10V Vout 90% t on t off tr td(off) tf VDD ( 0.5 rated VDS ) td(on) Vin 10% Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms LL VDS Vary tp to obtain required peak ID BVDSS 1 EAS = ---- LL IAS2 -------------------2 BVDSS -- VDD tp ID VDD Time VDS (t) RG DUT -10V tp C VDD ID (t) IAS BVDSS SFP9620 P-CHANNEL POWER MOSFET Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms + VDS DUT -IS L Driver RG VGS Compliment of DUT (N-Channel) VGS VDD • dv/dt controlled by “RG” • IS controlled by Duty Factor “D” VGS ( Driver ) Gate Pulse Width D = -------------------------Gate Pulse Period 10V Body Diode Reverse Current IS ( DUT ) IRM di/dt IFM , Body Diode Forward Current Vf VDS ( DUT ) Body Diode Forward Voltage Drop Body Diode Recovery dv/dt VDD TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ DISCLAIMER ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 TinyLogic™ UHC™ VCX™ FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.