SFRU9024

Advanced Power MOSFET FEATURES n Avalanche Rugged Technology n Rugged Gate Oxide Technology n Lower Input Capacitance n Improved Gate Charge n Extended Safe Operating Area n Lower Leakage Current : 10 µA (Max.) @ VDS = -60V n Lower RDS(ON) : 0.206 Ω (Typ.) SFR/U9024 BVDSS = -60 V RDS(on) = 0.28 Ω ID = -7.8 A D-PAK 2 1 3 1 I-PAK 2 3 1. Gate 2. Drain 3. Source Absolute Maximum Ratings Symbol VDSS ID IDM VGS EAS IAR EAR dv/dt PD Characteristic Drain-to-Source Voltage Continuous Drain Current (TC=25 C) Continuous Drain Current (TC=100 C) Drain Current-Pulsed Gate-to-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt o Total Power Dissipation (TA=25 C) * 2 O 1 O 1 O 3 O o o Value -60 -7.8 -5.5 1 O Units V A A V mJ A mJ V/ns W W W/ C o 31 ±30 155 -7.8 3.2 -5.5 2.5 32 0.26 - 55 to +150 Total Power Dissipation (TC=25 C) Linear Derating Factor Operating Junction and Storage Temperature Range Maximum Lead Temp. for Soldering Purposes, 1/8” from case for 5-seconds o TJ , TSTG TL o C 300 Thermal Resistance Symbol RθJC RθJA RθJA Characteristic Junction-to-Case Junction-to-Ambient * Junction-to-Ambient Typ. ---Max. 3.91 50 110 o Units C/W * When mounted on the minimum pad size recommended (PCB Mount). Rev. C SFR/U9024 Electrical Characteristics (TC=25oC unless otherwise specified) Symbol BVDSS ∆BV/∆TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd Characteristic Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coeff. Gate Threshold Voltage Gate-Source Leakage , Forward Gate-Source Leakage , Reverse Drain-to-Source Leakage Current Static Drain-Source On-State Resistance Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain(“Miller”) Charge Min. Typ. Max. Units -60 --2.0 ------------------0.04 ------3.7 465 140 40 11 21 29 20 15 2.9 6.0 ---4.0 -100 100 -10 -100 0.28 -600 215 60 30 50 65 50 19 --nC ns pF µA Ω S V o P-CHANNEL POWER MOSFET Test Condition VGS=0V,ID=-250µA See Fig 7 VDS=-5V,ID=-250µA VGS=-20V VGS=20V VDS=-60V VDS=-48V,TC=125 C VGS=-10V,ID=-3.9A VDS=-30V,ID=-3.9A 4 O 4 O o V/ C ID=-250µA V nA VGS=0V,VDS=-25V,f =1MHz See Fig 5 VDD=-30V,ID=-9.7A, RG=18 Ω See Fig 13 VDS=-48V,VGS=-10V, ID=-9.7A See Fig 6 & Fig 12 45 OO 45 OO Source-Drain Diode Ratings and Characteristics Symbol IS ISM VSD trr Qrr Characteristic Continuous Source Current Pulsed-Source Current Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge 1 O Min. Typ. Max. Units --------80 0.22 -7.8 -31 -3.8 --A V ns µC Test Condition Integral reverse pn-diode in the MOSFET TJ=25 C,IS=-7.8A,VGS=0V TJ=25 C,IF=-9.7A diF/dt=100A/µs 4 O o o O 4 Notes ; 1 O Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature 2 L=3.0mH, I =-7.8A, V =-25V, R =27Ω *, Starting T =25oC O AS DD G J 3 _ _ _ O ISD < -9.7A, di/dt < 250A/µs, VDD< BVDSS , Starting TJ =25oC 4 _ O Pulse Test : Pulse Width = 250µs, Duty Cycle< 2% 5 O Essentially Independent of Operating Temperature P-CHANNEL POWER MOSFET Fig 1. Output Characteristics VGS Top : -1 V 5 -1 V 0 - 8.0 V - 7.0 V - 6.0 V - 5.5 V - 5.0 V Bottom : - 4.5 V SFR/U9024 Fig 2. Transfer Characteristics -ID , Drain Current [A] -ID , Drain Current [A] 11 0 11 0 1 0 oC 5 10 0 2 oC 5 - 5 oC 5 1 -1 0 2 4 6 @Nts: oe 1 V =0V . GS 2 V =-0V . DS 3 us et 3 2 0 µs P l e T s .5 8 1 0 10 0 @Nts: oe 1 2 0 µs P l e T s .5 us et 2 T = 2 oC .C 5 1 -1 -1 0 1 0 10 0 11 0 -VDS , Drain-Source Voltage [V] -VGS , Gate-Source Voltage [V] Fig 3. On-Resistance vs. Drain Current 04 .0 Fig 4. Source-Drain Diode Forward Voltage -IDR , Reverse Drain Current [A] RDS(on) , [ Ω ] Drain-Source On-Resistance 03 .5 11 0 03 .0 V =-0V 1 GS 02 .5 02 .0 10 0 1 0 oC 5 2C 5 1 -1 0 o 01 .5 V =-0V 2 GS 01 .0 0 5 1 0 1 5 2 0 2 5 @ N t : T = 2 oC oe J 5 3 0 3 5 4 0 @Nts: oe 1 V =0V . GS 2 2 0 µs P l e T s .5 us et 05 . 10 . 15 . 20 . 25 . 30 . 35 . -ID , Drain Current [A] -VSD , Source-Drain Voltage [V] Fig 5. Capacitance vs. Drain-Source Voltage 80 0 C =C +C (C =sotd) iss gs gd ds h r e C =C +C oss ds gd C =C rss gd Fig 6. Gate Charge vs. Gate-Source Voltage 1 0 60 0 C oss 40 0 @Nts: oe 1 V =0V . GS 2 f=1Mz . H 20 0 C rss -VGS , Gate-Source Voltage [V] C iss Capacitance [pF] V =-2V 1 DS V =-0V 3 DS V =-8V 4 DS 5 @Nts:I =97A oe D -. 0 0 4 8 1 2 1 6 00 1 0 11 0 -VDS , Drain-Source Voltage [V] QG , Total Gate Charge [nC] SFR/U9024 Fig 7. Breakdown Voltage vs. Temperature 12 . 25 . P-CHANNEL POWER MOSFET Fig 8. On-Resistance vs. Temperature -BVDSS , (Normalized) Drain-Source Breakdown Voltage RDS(on) , (Normalized) Drain-Source On-Resistance 20 . 11 . 15 . 10 . 10 . @Nts: oe 1 V =-0V . GS 1 2 I =-. A . D 49 -0 5 -5 2 0 2 5 5 0 7 5 10 0 15 2 10 5 15 7 20 0 09 . @Nts: oe 1 V =0V . GS 2 I = - 5 µA . D 20 -0 5 -5 2 0 2 5 5 0 7 5 10 0 o 05 . 08 . -5 7 15 2 10 5 15 7 00 . -5 7 TJ , Junction Temperature [ C] TJ , Junction Temperature [oC] Fig 9. Max. Safe Operating Area -ID , Drain Current [A] Oeaini Ti Ae prto n hs ra i L m t d b R DS(on) s iie y Fig 10. Max. Drain Current vs. Case Temperature 8 -ID , Drain Current [A] 12 0 12 0 6 01m .s 11 0 1m 0s @Nts: oe 1 T = 2 oC .C 5 2 T = 1 0 oC .J 5 3 Snl Ple . ige us 1 -1 0 0 1 0 D C 1m s 4 10 0 2 11 0 0 2 5 5 0 7 5 10 0 15 2 10 5 -VDS , Drain-Source Voltage [V] Tc , Case Temperature [oC] Fig 11. Thermal Response Thermal Response D=0.5 10 0 0.2 0.1 0.05 @ Notes : 1. Zθ J C (t)=3.91 o C/W Max. 2. Duty Factor, D=t1 /t2 3. TJ M -TC =PD M *Zθ J C (t) P. DM t1. t2. Z (t) , 10- 1 0.02 0.01 single pulse θ JC 10- 5 10- 4 10- 3 10- 2 10- 1 100 101 t 1 , S quare Wave Pulse Duration [sec] P-CHANNEL POWER MOSFET Fig 12. Gate Charge Test Circuit & Waveform SFR/U9024 “ Current Regulator ” 50KΩ 12V 200nF 300nF Same Type as DUT VGS Qg -10V VDS VGS DUT -3mA Qgs Qgd R1 Current Sampling (IG) Resistor R2 Current Sampling (ID) Resistor Charge Fig 13. Resistive Switching Test Circuit & Waveforms RL Vout Vin RG DUT -10V Vout 90% t on t off tr td(off) tf VDD ( 0.5 rated VDS ) td(on) Vin 10% Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms LL VDS Vary tp to obtain required peak ID BVDSS 1 EAS = ---- LL IAS2 -------------------2 BVDSS -- VDD tp ID VDD Time VDS (t) RG DUT -10V tp C VDD IAS BVDSS ID (t) SFR/U9024 Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms P-CHANNEL POWER MOSFET + VDS DUT -IS L Driver RG VGS Compliment of DUT (N-Channel) VGS VDD • dv/dt controlled by “RG” • IS controlled by Duty Factor “D” VGS ( Driver ) Gate Pulse Width D = -------------------------Gate Pulse Period 10V Body Diode Reverse Current IS ( DUT ) IRM di/dt IFM , Body Diode Forward Current Vf VDS ( DUT ) Body Diode Forward Voltage Drop Body Diode Recovery dv/dt VDD TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production Rev. I1