SG1577ASY

SG1577A — Dual Synchronous DC/DC Controller September 2009 SG1577A Dual Synchronous DC/DC Controller Features Integrated Two Sets of MOSFET Drivers Two Independent PWM Controllers Constant Frequency Operation: Free-running Fixed Frequency Oscillator Programmable: 61kHz to 340kHz Maximum Input Supply Voltage: 15V Programmable Output as Low as 0.7V Internal Error Amplifier Reference Voltage: 0.7V±1.5% Two Soft-Start / EN Functions Programmable Over-Current Protection (OCP) 30V HIGH Voltage Pin for Bootstrap Voltage Output Over-Voltage Protection (OVP) 20-Pin SOP Description The SG1577A is a high-efficiency, voltage-mode, dualchannel, synchronous DC/DC PWM controller for two independent outputs. The two channels are operated out of phase. The internal reference voltage is trimmed to 0.7V±1.5%. It is connected to the error amplifier’s positive terminal for voltage feedback regulation. The soft-start circuit ensures the output voltage can be gradually and smoothly increased from zero to its final regulated value. The soft-start pin can also be used for chip-enable function. When two soft-start pins are grounded, the chip is disabled and the total operation current can be reduced to under 0.7mA. The fixed-frequency is programmable from 60kHz to 340kHz. The Over-Current Protection (OCP) level can be programmed by an external current sense resistor. It has two integrated sets of internal MOSFET drivers. SG1577A is available in a 20-pin SOP package. Applications CPU and GPU Vcore Power Supply Power Supply Requiring Two Independent Outputs Ordering Information Part Number SG1577ASY Operating Temperature Range -40°C to +105°C Eco Status Green Package 20-Lead, Small Outline Package (SOP-20) Packing Method Tape & Reel For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 www.fairchildsemi.com SG1577A — Dual Synchronous DC/DC Controller Application Diagram Figure 1. Typical Application Internal Block Diagram Figure 2. © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 Functional Block Diagram www.fairchildsemi.com 2 SG1577A — Dual Synchronous DC/DC Controller Marking Diagram 20 ZXYTT SG1577A TPM 1 F: Fairchild Logo Z: Assembly Plant Code X: Year Code Y: Week Code TT: Die Run Code T: S = SOP P: Y=Green Package M: Mask Version SOP-20 © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 www.fairchildsemi.com 3 SG1577A — Dual Synchronous DC/DC Controller Pin Configuration Figure 3. SOP-20 Pin Configuration (Top View) Pin Definitions Name RT Pin # 1 Type Description Switching frequency programming pin. An external resistor connecting this pin to GND can program the switching frequency. The switching Frequency Select frequency is 61kHz when RT is open and becomes 340kHz when RT is shorted to ground. Feedback Compensation Soft Start/Enable Over Current Protection Boost Supply High-Side Drive Switch Node Low-Side Drive Driver Ground Power Supply Low-Side Drive Switch Node High-Side Drive Boost Supply Over-Current Protection Soft-Start/Enable Compensation Feedback Analog Ground Inverting input of the error amplifier. It is normally connected to the switching power supply output through a resistor divider. Output of the error amplifier and input to the PWM comparator. It is used for feedback loop compensation. A 35/15µA internal current source charging an external capacitor for softstart. Pull down this pin and pin 17 to disable the chip. Over-current protection for high-side MOSFET. Connect a resistor from this pin to the high-side supply voltage to program the OCP level. Supply for high-side driver. Connect to the internal bootstrap circuit. Channel 1, high-side MOSFET gate driver pin. Switch-node connection to inductor. For channel 1 high-side driver’s reference ground. Low-side MOSFET gate driver pin. Driver circuit reference. Connect to low-side MOSFET GND. Supply voltage input. Low-side MOSFET gate driver pin. Switch-node connection to inductor. For channel 2, high-side driver’s reference ground. Channel 2 high-side MOSFET gate driver pin. Supply for high-side driver. Connect to the internal bootstrap circuit. Over-current protection for the high-side MOSFET. Connect a resistor from this pin to the high-side supply voltage to program the OCP level. A 35/15µA internal current source charging an external capacitor for soft-start. Pull down this pin and pin 4 to disable the chip. Output of the error amplifier and input to the PWM comparator. It is used for feedback-loop compensation. Inverting input of the error amplifier. It is normally connected to the switching power supply output through a resistor divider. The reference of internal control circuits. IN1 COMP1 SS1/ENB CLP1 BST1 DH1 CLN1 DL1 PGND VCC DL2 CLN2 DH2 BST2 CLP2 SS2/ENB COMP2 IN2 GND 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 www.fairchildsemi.com 4 SG1577A — Dual Synchronous DC/DC Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are given with respect to the network ground terminal. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Symbol VCC BST1(or 2) – CLN1(or 2) CLN1(or 2) – GND BST1(or 2) – GND DH1(or 2) – CLN1(or 2) CLN1(or 2), DL1(or 2) PGND ΘJA TJ TSTG ESD PGND to GND Parameter Supply Voltage, VCC to GND BST1(2) to CLN1(2) CLN1(2) to GND for 100ns Transient BST1(2) to GND for 100ns Transient Min. Max. 16 16 Unit V V V V V V V °C/W °C °C kV -4 18 30 16 -0.3 VCC+0.3 ±1 90 Thermal Resistance, Junction-Air Operating Junction Temperature Storage Temperature Range Electrostatic Discharge Protection Level Human Body Model (HBM) Charged Device Model (CDM) -40 -65 +125 +150 2 1 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC TA Supply Voltage Parameter Operating Ambient Temperature Min. -40 Max. +15 +105 Unit V °C © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 www.fairchildsemi.com 5 SG1577A — Dual Synchronous DC/DC Controller Electrical Characteristics VCC=12V, TA =25°C, unless otherwise noted. Symbol VCC UVLO VCC_ON VCC_HYS Oscillator fosc fosc,rt DON_MAX VREF △VREF AVOL BW ISOURCE ISINK VH RAMP_Peak V RAMP_Valley ISOURCE_1 ISOURCE_2 st (1) Parameter Turn-On Threshold UVLO Hysteresis Conditions VCC Ramp-Up VCC Ramp-Down RRT=OPEN RRT=GND 20kΩ＜RRT Min. 9.5 1.5 55 308 -10 85 Typ. 10.0 2.0 61 340 90 0.7000 0.03 77 3.5 Max. 10.5 2.5 67 372 10 95 0.7105 Unit V V Oscillator Frequency Total Accuracy Maximum Duty Cycle Internal Reference Voltage VREF Temperature Coefficient Open-loop Voltage Gain Unity Gain Bandwidth Output Source Current Output Sink Current The Peak of VRAMP The Valley of VRAMP 1 Soft-start Charge Current 2 nd st KHz % % V mV/ C dB MHz o Error Amplifier VCC=8V, VCC=15V TA=0~85 C o 0.6895 IN1=IN2=0.6V IN1=IN2=0.8V Gate Output=DON_MAX No Gate Output VCLP＜VCLN , VSS_Transition＞VSS VCLP＜VCLN , VSS_Transition＜VSS ISOURCE_1 Transit to ISOURCE_2 See Figure 4 VCLP＞VCLN VCC=12V st nd 60 250 2.45 1.05 28 13 1.40 80 400 2.8 1.2 35 16 1.42 50 100 550 3.15 1.35 42 19 1.44 µA µA V V µA µA V µA Two-Stage Soft-Start nd Soft-start Charge Current VSS_Transition ISINK Protections IOCSET TOT TOT_hys VOVP Output IDH RDH IDL RDL TDT (2) Soft-start Transition Point Soft-start Discharge Current OC Sink Current Over-Temperature Over-Temperature Hysteresis Over-Voltage Protection of IN High-Side Current Source High-Side Sink Resistor Low-Side Current Source Low-Side Sink Resistor Dead Time Operating Supply Current Standby Current (Disabled) 90 120 150 20 150 µA °C °C VOVP/VIN VBST - VCLN=12V, VDH - VCLN=6V VBST - VCLN=12V VCC=12V, VDL =6V VCC=12V VCC=12V, DH & DL=1000pF VCC=12V, No load SS1/ENB=SS2/ENB=0V 118 1.0 1.0 50 3.3 122 1.8 2.8 1.8 2.8 70 4.3 0.7 126 % A 3.8 3.8 90 5.3 1.0 Ω A Ω ns mA mA Total Operating Current ICC_OP ICC_SBY Notes: 1. Not tested in production, 30pcs sample. 2. When VDL falls less than 2V relative to VDH rising to 2V. © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 www.fairchildsemi.com 6 SG1577A — Dual Synchronous DC/DC Controller Timing Diagrams Figure 4. Timing Chart of Two-Stage Soft-Start © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 www.fairchildsemi.com 7 SG1577A — Dual Synchronous DC/DC Controller Typical Performance Characteristics Unless otherwise noted, values are for VCC=12V, TA=+25°C, CSS1/ENB=150nF and CSS2/ENB=168nF. Figure 5. Power On at 0.3A Load Figure 6. Power On at 3.6A Load Figure 7. Power On at 9A Load Figure 8. Power On at 18A Load Figure 9. Power Off with 0.3A Load Figure 10. Power Off with 18A Load © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 www.fairchildsemi.com 8 SG1577A — Dual Synchronous DC/DC Controller Typical Performance Characteristics (Continued) Unless otherwise noted, values are for VCC=12V, TA=+25°C, CSS1/ENB=150nF and CSS2/ENB=168nF. Figure 11. Phase Shift at 0.3A Load Figure 12. Phase Shift at 18A Load Figure 13. Dead Time at 0.3A Load (Rising Edge) Figure 14. Dead Time at 0.3A Load (Falling Edge) Figure 15. Dead Time at 18A Load (Rising Edge) Figure 16. Dead Time at 18A Load (Falling Edge) © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 www.fairchildsemi.com 9 SG1577A — Dual Synchronous DC/DC Controller Typical Performance Characteristics (Continued) Unless otherwise noted, values are for VCC=12V, TA=+25°C, CSS1/ENB=150nF and CSS2/ENB=168nF. Figure 17. Load Transient Response (Step-Up) 20kΩ /22nF in Compensation Loop Figure 18. Load Transient Response (Step-Down) 20kΩ /22nF in Compensation Loop Figure 19. Over-Current Protection (OCP) Figure 20. Over-Current Protection (“Hiccup” Mode) 150 Iocset 1 140 IO C S E T ( u A ) 130 120 110 100 90 -40 -25 -10 5 20 35 o Iocset 2 50 65 80 95 Temperature ( C) Figure 21. Over-Voltage Protection (OVP) © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 Figure 22. IOCSET vs. Temperature www.fairchildsemi.com 10 SG1577A — Dual Synchronous DC/DC Controller Functional Description The SG1577A is a dual-channel voltage-mode PWM controller. It has two sets of synchronous MOSFET driving circuits. The two channels are running 180degrees out of phase. The following descriptions highlight the advantages of the SG1577A design. compensation externally. Non-inverting inputs are internally tied to a fixed 0.7V ± 1.5% reference voltage. Oscillator Operation The SG1577A has a frequency-programmable oscillator. The oscillator is running at 61kHz when the RT pin is floating. The oscillator frequency can be adjusted from 61kHz up to 340kHz by an external resistor RRT between RT pin and the ground. The oscillator generates a sawtooth wave that has 90% rising duty. Sawtooth wave voltage threshold is from 1.2V to 2.8V. The frequency of oscillator can be programmed according to the following equation: fOSC, RT(kHz) = 61kHz + 8522 / RRT(kΩ) Soft Start An internal start-up current (35/15µA) flows out of SS/EN pin to charge an external capacitor. During the startup sequence, SG1577A isn’t enabled until the SS/ENB pin is higher than 1.2V. From 1.2V to (1.2 + 1.6 x DON / DON_MAX) V, the PWM duty cycle gradually increases following the SS/ENB pin voltage to bring output rising. After (1.2 + 1.6 x DON / DON_MAX) V, the soft-start period ends and SS/ENB pin continually rises to 4.8V. When input power is abnormal, the external capacitor on the SS pin is shorted to ground and the chip is disabled. 5 CSS1 × (1.4V - 1.2V) = 35uA × t1; CSS1 × (1.2V + 1.6 × 12 - 1.4V) = 15µA × t 2 0.9 ; t1 + t 2 = t SS1 (3) Output Driver The high-side gate drivers need an external bootstrapping circuit to provide the required boost voltage. The highest gate driver’s output (15V is the allowed) on high-side and low-side MOSFETs forces external MOSFETs to have the lowest RDS(ON), which results in higher efficiency. 3.3 CSS2 × (1.4V - 1.2V) = 35µA × t1; CSS2 × (1.2V + 1.6 × 12 - 1.4V) = 15µA × t 2 0.9 ; t1 + t 2 = t SS2 (1) CSS1 × 1.2V = 35µA × t 3; ; t 4 - t 3 = t time - shift CSS2 × 0.3V CSS2 × (1.2V - 0.3V) + = t4 15µA 35µA Over-Temperature Protection (OTP) The device is over-temperature protected. When chip o temperature is over 150 C, the chip enters tri-state o (high-side driver is turned off). The hysteresis is 20 C. Over-Current Protection (OCP) Over-current protection is implemented by sensing the voltage drop across the drain and the source of external high-side MOSFET. Over-current protection is triggered when the voltage drop on external high-side MOSFET’s RDS(ON) is greater than the programmable current limit voltage threshold. 120µA flowing through an external resistor between input voltage and the CLP pin sets the threshold of current limit voltage. When over-current condition is true, the system is protected against the cycle-by-cycle current limit. A counter counts a series of over-current peak values to eight cycles; the soft-start capacitor is discharged by a 50µA current until the voltage on SS pin reaches 1.2V. During the discharge period, the high-side driver is turned off and the lowside driver is turned on. Once the voltage on SS/ENB pin is under 1.2V, the normal soft-start sequence is initiated and the 35/15µA current charges the soft-start capacitor again. IL(OCP)= [(RSENSE x IOCSET + VOFFSET) / RDS(ON) (VIN - VOUT) x VOUT / (fOSC x LOUT x VIN x 2) ] (2) Type II Compensation Design (for Output Capacitors with High ESR) SG1577A is a voltage-mode controller; the control loop is a single voltage feedback path, including an error amplifier and PWM comparator, as shown in Figure 23. To achieve fast transient response and accurate output regulation, an adequate compensator design is necessary. A stable control loop has a 0dB gain crossing with -20dB/decade slope and a phase margin greater than 45°. where VOFFSET ( ≒ 10mV) is the offset voltage contributed by the internal OCP comparator. Error Amplifier The IN1 and IN2 pins are connected to the corresponding internal error amplifier’s inverting input and the outputs of the error amplifiers are connected to the corresponding COMP1 and COMP2 pins. The COMP1 and COMP2 pins are available for control-loop © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 Figure 23. Closed Loop www.fairchildsemi.com 11 SG1577A — Dual Synchronous DC/DC Controller 1. Modulator Frequency Equations The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This transfer function is dominated by a DC gain and the output filter (LO and CO) with a double-pole frequency at fLC and a zero at fESR. The DC gain of the modulator is the input voltage (VIN) divided by the peak-to-peak oscillator voltage ΔVRAMP(=1.6V). The first step is to calculate the complex conjugate poles contributed by the LC output filter. The output LC filter introduces a double pole, -40dB / decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. The resonant frequency of the LC filter expressed as: fP(LC) = 1 2π × L O × C O fP1 = 0 fZ1 = fP2 = 1 2π × R 2 × C 2 1 2π × R 2 × (C1 // C2 ) (6) Figure 25 shows the DC-DC converter gain vs. frequency. The compensation gain uses external impedance networks ZC and Zf to provide a stable, highbandwidth loop. High crossover frequency is desirable for fast transient response, but often jeopardizes system stability. To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency. Place the zero at 75% of the LC filter resonant frequency. Crossover frequency should be higher than the ESR zero, but less than 1/5 of the switching frequency. The second pole should be placed at half the switching frequency. (4) The next step of compensation design is to calculate the ESR zero. The ESR zero is contributed by the ESR associated with the output capacitance. Note that this requires that the output capacitor should have enough ESR to satisfy stability requirements. The ESR zero of the output capacitor is expressed as: fZ(ESR ) = 1 2π × CO × ESR (5) 2. Compensation Frequency Equations The compensation network consists of the error amplifier and the impedance networks ZC and Zf, as Figure 24 shows. Figure 25. Bode Plot Figure 24. Compensation Loop © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 www.fairchildsemi.com 12 SG1577A — Dual Synchronous DC/DC Controller Layout Considerations Layout is important in high-frequency switching converter design. If designed improperly, PCB can radiate excessive noise and contribute to converter instability. Place the PWM power stage components first. Mount all the power components and connections in the top layer with wide copper areas. The MOSFETs of buck, inductor, and output capacitor should be as close to each other as possible to reduce the radiation of EMI due to the high-frequency current loop. If the output capacitors are placed in parallel to reduce the ESR of capacitor, equal sharing ripple current should be considered. Place the input capacitor near the drain of high-side MOSFET. In multi-layer PCB, use one layer as power ground and have a separate control signal ground as the reference for all signals. To avoid the signal ground being affected by noise and to achieve the best load regulation, it should be connected to the ground terminal of output. Follow the below guidelines for best performance: A two-layer printed circuit board is recommended. Use the bottom layer of the PCB as a ground plane and make all critical component ground connections through vias to this layer. Keep the metal running from the CLNx terminal to the output inductor short. Use copper-filled polygons on the top (and bottom, if two-layer PCB) circuit layers for the CLN node. The small-signal wiring traces from the DLx and DHx pins to the MOSFET gates should be kept short and wide enough to easily handle the several amps of drive current. The critical, small-signal components include any bypass capacitors (SMD-type of capacitors applied at VCC and SSx/ENB pins), feedback components (resistor divider), and compensation components (between INx and COMPx pins). Position those components close to their pins with a local, clear, GND connection or directly to the ground plane. Place the bootstrap capacitor near the BSTx and CLNx pins. The resistor on the RT pin should be near this pin and the GND return should be short and kept away from the noisy MOSFET’s GND (which is shorted together with IC’s PGND pin to GND plane on back side of PCB). Place the compensation components close to the INx and COMPx pins. The feedback resistors for both regulators should be located as close as possible to the relevant INx pin with vias tied straight to the ground plane as required. Minimize the length of the connections between the input capacitors, CIN, and the power switchers (MOSFETs) by placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible and make the GND returns short (from the source of lower MOSFET to VIN capacitor GND). Position the output inductor and output capacitors between the upper MOSFET and lower MOSFET and the load. AGND should be on the clearer plane and kept away from the noisy MOSFET GND. PGND should be short, together with MOSFET GND, then through vias to GND plane on the bottom of PCB. © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 www.fairchildsemi.com 13 SG1577A — Dual Synchronous DC/DC Controller Physical Dimensions 13.00 12.60 11.43 20 B 11 A 9.50 10.65 7.60 10.00 7.40 2.25 1 PIN ONE INDICATOR 0.51 0.35 0.25 M 1.27 CBA 10 1.27 0.65 LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A C 0.33 0.20 0.10 C SEATING PLANE 0.75 0.25 (R0.10) (R0.10) 8° 0° X 45° 0.30 0.10 NOTES: UNLESS OTHERWISE SPECIFIED GAGE PLANE 0.25 1.27 0.40 (1.40) A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.5M-1994 E) LANDPATTERN STANDARD: SOIC127P1030X265-20L F) DRAWING FILENAME: MKT-M20BREV3 SEATING PLANE DETAIL A SCALE: 2:1 Figure 26. 20-Lead Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 www.fairchildsemi.com 14 SG1577A — Dual Synchronous DC/DC Controller © 2009 Fairchild Semiconductor Corporation SG1577A • Rev. 1.0.0 www.fairchildsemi.com 15