SG6902

www.fairchildsemi.com AN-6902 Applying SG6902 to Control a CCM PFC and Flyback/PWM Power Supply Summary This application note shows a step-by-step design to a 120W/24V power adapter. The equations also can be applied to different output voltages and wattages. Description SG6902 is designed for power supplies that consist of boost PFC and flyback PWM. It requires few external components to achieve green-mode operation and versatile protections and compensations. The proprietary interleave switching synchronizes the PFC and PWM stages and reduces switching noise. At light loads, PFC stage is turned off to save power and the PWM switching frequency is decreased in response to the load. For PFC stage, the proprietary multi-vector control scheme provides a fast transient response in a low-bandwidth PFC loop. The overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, SG6902 shuts off the switching to protect the power supply and its load. For the flyback PWM stage, the synchronized slope compensation ensures the stability of the current loop. “Hiccup” operation limits a maximum output power during the overload situations. The difference between members of this family are shown in the table below. Parameter Start Threshold Voltage Minimum Operating Voltage The Interval of OPFC Lags Behind OPWM at Startup PFC On/Off OTP Soft-Start Features Interleaved PFC/PWM Switching Green-Mode PFC/PWM Switching No PFC Switching at Light Loads for Power Saving Innovative Switching Charge Multiplier-divider Low Startup and Operating Current Innovative Switching Charge Multiplier-divider Multi-vector Control for Improved PFC Output Transient Response Average-Current-Mode Control for PFC Programmable Two-Level PFC Output Voltage to Achieve the Best Efficiency PFC Over-voltage and Under-voltage Protections PFC and PWM Feedback Open-loop Protection Cycle-by-cycle Current Limiting for PFC/PWM Slope Compensation for PWM Maximum Power Limit for PWM Brownout Protection Over Temperature Protection Power-on Sequence Control and Soft-start 20-Pin SOP and SSOP Packages SG6902 16V 10V 11.5ms O O O SG6901A 12V 10V 11.5ms X O O © 2007 Fairchild Semiconductor Corporation Rev. 1.2.1 • 5/1/08 www.fairchildsemi.com AN-6902 APPLICATION NOTE Pin Configuration Figure 1. Pin Configuration Typical Application Figure 2. Typical Application © 2007 Fairchild Semiconductor Corporation Rev. 1.2.1 • 5/1/08 www.fairchildsemi.com 2 AN-6902 APPLICATION NOTE Block Diagram Figure 3. Block Diagram © 2007 Fairchild Semiconductor Corporation Rev. 1.2.1 • 5/1/08 www.fairchildsemi.com 3 AN-6902 APPLICATION NOTE PFC Section Power-On Sequence SG6902 is active when the line voltage is higher than the brownout threshold. The PWM stage is switching first, then, following an 11.5ms delay time after FBPWM voltage is higher than a PFC turn-on threshold voltage, the PFC stage is enabled. Because the capacitor includes ±20% variation, the capacitor 100µF is chosen. PFC Inductor The switching frequency fS, output power POUT, efficiency n, maximum ripple current ΔI, and minimum input voltage VIN.min should be defined before determining the inductance of PFC inductor. The following equations are utilized to determine the inductance of the PFC inductor. Normally the maximum ripple current is 20% ~ 30% of maximum input current. ΔI = 2 (POUT / η × 0.3 ) VIN(MIN) Figure 4. Interleaving Switching Boost Rectifier and Switch The fast reverse-recovery time of the boost diode is required to reduce the power losses and the EMI. A 500V voltage rating is chosen to withstand 400V boosts potential. The average current and peak currents flow through the boost diode and the switch, respectively, and are given by: IAVG = 2 × 2 × POUT / η π × VRMS(Brownout ) 2 × 2 × 120 / 0.8 = 1 .8 A π × 75 POUT / η VRMS(Brownout ) 120 / 0.8 = 2.82 A 75 (1) V ×2 D = 1 − IN. min VO (2) IAVG = (7) V =L di dt (3) IPEAK = 2 × IPEAK = 2 × V × 2 × Dmax / fs L = IN.min ΔI (4) Oscillation and Green Mode The resistor RI connected from the RI to GND pin programs the switching frequency of SG6902. For a 120W adapter power, η= 0.85, VIN(MIN) = 90VAC, fS = 65KHz, VO = 250V, ΔI = 0.66A, D = 0.49, L = 0.4mH. fS = 1560 (KHz ) RI ( KΩ ) (8) PFC Capacitor An advantage of using interleaving switching of PFC and PWM stage is to reduce the switching noise. The ESR requirement of boost capacitor is relaxed. The boost capacitor value is chosen to remain a hold-up time of output voltage in the event line voltage is removed. CO = For example, a 24kΩ resistor RI results in a 65kHz switching frequency. The recommended range for the switching frequency is 33kHz ~ 100kHz. SG6902 provides an off-time modulation to reduce the switching frequency in light-load and no-load conditions. The feedback voltage of FBPWM pin is taken as reference. When the feedback voltage is lower than about 2.1V, the switching frequency decreases accordingly. Most of losses in a switching-mode power supply are proportional to the switching frequency; therefore, the off-time modulation reduces the power consumption of the power supply in light-load and no-load conditions. For a typical case of RI = 24KΩ, the switching frequency is 65kHz at nominal load and decreases to 20kHz at light load. The switching signal is disabled if the switching frequency falls below 20KHz, which avoids acoustic noise. For stability reasons, a capacitor connecting the RI pin to GND is not suggested. www.fairchildsemi.com 4 (VO(normal ) − Vripple )2 − VO.min2 2 × (POUT /ηPWM ) × t hold -up (5) where VO.min is the minimum output voltage in accordance with the requirement of the specification. For a 120W power supply, the capacitor is determined as: CO > 2 × (120 W / 0.85 ) × 15ms (250 − 20 )2 − 602 = 86 μF (6) © 2007 Fairchild Semiconductor Corporation Rev. 1.2.1 • 5/1/08 AN-6902 APPLICATION NOTE fs 20KHz 2.1 FBPWM(V) Figure 5. Switching Frequency vs. FB Voltage To save power, the PFC stage is enabled only when the feedback voltage of the FBPWM pin is higher than a threshold voltage VTH. The threshold voltage VTH is 2.1V to 2.45V at low line voltage input, 1.95V at high line voltage. The threshold voltage VTH determines an output power threshold to turn on/off the PFC stage for the power saving. The output power POUT can be expressed as: POUT = Figure 6. Linear Range Line Voltage Detection (VRMS) Figure 6 shows a resistive divider with low-pass filter connected to the VRMS pin for line-voltage detection. The VRMS input is used for the PFC multiplier and brownout protection. For a sine wave input voltage, the voltage on the VRMS pin is directly proportional to input voltage. To achieve the brownout protection, the PFC stage is disabled after a 195ms delay once the VRMS voltage drops below 0.8V. The PWM stage is protected through the open-loop detection on the FBPWM pin when the output voltage of the PFC stage is too low. After that, SG6902 turns off. When VRMS voltage is higher than 0.98V, the SG6902 restarts in accordance with power-on sequence of PFC and PWM stages. For example, a brownout protection is set as 75VAC. The RRMS and RI can be determined as: VIN(MEAN ) = VIN × 2 × 2 η × (VIN × t ON )2 2 × LP × t (9) ⎫ ⎧ V ⎪ ⎪ VIN(PEAK ) VFB = 1.2 V + 3 × ⎨ × RS × t ON + SL × t ON ⎬ LP t ⎪ ⎪ ⎭ ⎩ (10) where VSL is a synchronized 0.5V ramp. Equation 10 shows that, through the feedback loop, the on-time tON changes in response to the change of the switching period t and/or the inductance LP (the primary inductance of the transformer) for providing a same output power. Because the feedback voltage VFB controls the on-time tON, a lower VFB causes a narrow on-time tON. Changing the switching frequency (the switching period t) and the inductance LP, affects the output power threshold to on/off the PFC stage. IAC Signal Figure 6 shows that the IAC pin is connected to the input voltage via a resistor. A current IAC is used for PFC multiplier. IAC(PEAK ) ≈ VIN(PEAK ) R AC π (13) (14) VRMS = 2 R1 × VIN × 2 × π R1 + RRMS (11) The threshold of VRMS = 0.8V. If RRMS = 4.8MΩ and VIN = 75VAC, the value of R1 is 56.8KΩ. For wide range input: VIN(PEAK ) = 264 V × 2 = 374 V (12) The linear range of IAC is 0~360µA. A 1.2M resistor is suggested for a wide input range (90VAC ~ 264VAC). © 2007 Fairchild Semiconductor Corporation Rev. 1.2.1 • 5/1/08 www.fairchildsemi.com 5 AN-6902 APPLICATION NOTE PFC Operation Cycle-by-cycle Current Limiting SG6902 provides cycle-by-cycle current limiting for both PFC and PWM stages. Figure 8 shows the peak current limit for the PFC stage. The switching signal of PFC stage is turned off immediately once the voltage on ISENSE pin goes below the threshold voltage VPK. The voltage of VRMS determines the threshold voltage VPK. The correlation of the threshold voltage VPK and VRMS is shown in Figure 8. The amplitude of the constant current IP shown in Figure 8 is determined by a reference current IT, in accordance with the following equation as: Ip = 2 × IT = 2 × 1 .2 V RI Figure 7. Current Output The current source output from the switching charge multiplier/divider can be expressed as: I × VEA IMO = K × AC ( μA ) VRMS 2 (19) (15) Therefore, the peak current of the IS can be expressed as: According to Figure 7, the current output from IMP pin, IMP, is the summation of IMO and IMR1. The resistor R2 is equipped as same as R3. The constant current source IMR1 is identical with IMR2. They are used to bias (pull HIGH) the operating point of the IMP and IPFC pins since the voltage across RS goes negative with respect to ground. Through the differential amplification of the signal across RS, a better noise immunity is acjoeved. The output of IEA compared with an internal sawtooth generates a switching signal for PFC. Through the feedback loop of the average current control mode, the input current IS is proportional to IMO: IMO × R 2 = IS × RS (I × RP ) − 0.2V IS _ PEAK = P RS (20) Figure 8. Current Limit (16) Multi-vector Error Amplifier To achieve good power factor, the voltage for VRMS and VEA should be kept as DC-value according to Equation 14. In other words, a low-pass RC filtering for VRMS and a narrow bandwidth (lower than the line frequency) of PFC voltage loop are suggested to achieve better input current shaping. The trans-conductance error amplifier has output impedance RO (>90kΩ). A capacitor CEA (1µF ~ 10µF) is suggested to connect from the output of the error amplifier to ground (Figure 9). A dominant pole f1 of the PFC voltage loop is shown as: f1 = 1 2π × RO × CEA According to this equation, the minimum value of R2 and maximum value of RS can be determined. The IMO should be estimated under its specified maximum value. A concern in determining the value of the sense resistor RS includes low-resistance RS reduces the power consumption, but high-resistance RS provides high resolution to achieve low input current THD (total harmonic distortion). Using a current transformer (CT) instead of RS improves the efficiency for high-power converters.For a 120W adapter, the power consumption of RS = 0.36Ω is: ⎛ 120 W / 0.85 ⎞ PRS = ⎜ ⎟ × 0.36 = 0.885 W 90 ⎝ ⎠ 2 (21) (17) determined as The average total input power can be expressed as: PIN = VIN(RMS ) × IIN(RMS ) ∞VRMS × IMO I × VEA ∞VRMS × AC VRMS 2 ∞VRMS × VIN × VEA R AC VRMS 2 ∞VEA R2 and R3 can be (the brownout threshold is 75V): 120W/0.8 IMAX = × 2 = 2.83A 75V R S × IMAX IMO = R2 0.36 × 2.83 IMO = = 308 μ0 3.3K (18) (22) The results show that RS, R2, and R3 values are fit for providing 120W output. © 2007 Fairchild Semiconductor Corporation Rev. 1.2.1 • 5/1/08 www.fairchildsemi.com 6 AN-6902 APPLICATION NOTE Determine the resistor divider ratio RA/RB: RA V = O −1 RB 3 R A 250 = − 1 = 82 .33 RB 3 (25) (26) Assume RA = 3MΩ, RB = 36.5KΩ, and RC = 60KΩ. Refer to Figure 10. At high line input, maximum output voltage is: ⎛ RA ⎞ ⎟ VO(MAX ) = 3.15× = ⎜ ⎜ R // R + 1⎟ = 420 V C ⎝B ⎠ (27) Figure 9. Multi-vector Error Amplifier Another circuit provides further over-voltage protection to inhibit the PFC switching once the feedback voltage exceeds the 3.25V the output voltage is clamped at: ⎛ RA ⎞ ⎟ VO(OVP ) = 3.25 × ⎜ ⎜ R // R + 1⎟ = 433 V C ⎝B ⎠ Equation 22 shows the output of the voltage error amplifier, VEA, controls the total input power and the power delivered to the load. Although the PFC stage has a low bandwidth voltage loop for better input power factor, the innovative multi-vector error amplifier provides a fast transient response to clamp the overshoot and undershoot of PFC output voltage. Figure 10 shows the block diagram of the multi-vector error amplifier. When the variation of the feedback voltage (FBPFC) exceeds ±5% of the reference voltage (3V), the trans-conductance error amplifier programs its output current to speed up the loop response. If RA is open circuit, SG6902 is turned off immediately to prevent over-voltage on the output capacitor. (28) VO (PFC) + VEA 3V FBPFC RA RC RANGE SG69XX RB Two-level PFC Output voltage For universal input (90VAC ~ 264VAC), the output voltage of PFC is usually designed to 250V at low line and 400V at high line. This improves efficiency of the power converter for low-line input. The RANGE pin (opendrain) is used for the two-level output voltage setting. Figure 10 shows the RANGE output that programs the PFC output voltage. The RANGE output is shorted to ground when the VRMS voltage exceeds 1.95V. It is a high-impedance output (open) whenever the VRMS voltage drops below 1.6V. The output voltages can be determined using below equations: Range = Open ⇒ VO = R A + RB × 3V RB R A + (RB // RC ) × 3V (RB // RC ) Figure 10. Feedback Voltage of PFC PWM SECTION Soft-starting the PWM stage The soft-start pin controls the rising time of the output voltage and prevents the overshoot during power on. The soft-start capacitor value for the soft-start period tSS is given by: I CSS = t SS × SS VOZ (29) (23) where VOZ is the zero-duty threshold of FBPWM voltage. Range = GND ⇒ VO = (24) © 2007 Fairchild Semiconductor Corporation Rev. 1.2.1 • 5/1/08 www.fairchildsemi.com 7 AN-6902 APPLICATION NOTE Leading-Edge Blanking (LEB) A voltage signal develops on the current-sense resistor RS represents the switching current of MOSFET. Each time the MOSFET turns on, a spike, caused by the diode reverse recovery time and by the parasitic capacitances of the MOSFET, appears on the sensed signal. The SG6902 has a build-in leading-edge blanking time of about 350ns to avoid premature termination of MOSFET by the spike. Only a small-value RC filter (e.g. 100Ω + 47pF) is required between the IPWM pin and RS to prevent negative spike into the IPWM pin. A non-inductive resistor for the RS is recommended. Figure 12. Current Limit and Slope Compensation SG6841 Gate Blanking Circuit Sense Output Driver of OPFC and OPWM SG6902’s OPFC and OPWM is fast totem-pole gate driver that is able to directly drive external MOSFET. An internal Zener diode clamps the driver voltage under 18V to protect MOSFET from over-voltage damage. VDD ON/OFF Driver 18V Gate Figure 11. Turn-on Spike Flyback PWM and Slope Compensation As shown in Figure 12, peak-current-mode control is utilized for flyback PWM. The SG6902 inserts a synchronized 0.5V ramp at the beginning of each switching cycle. This built-in slope compensation reduces the current loop gain and ensures stable operation for current-mode operation. When the IPWM voltage, across the sense resistor, reaches the threshold voltage, 0.65V or 0.7V selected by RANGE, the OPWM turns off after a small propagation delay, tPD-PWM. This propagation delay introduces an additional current proportional to TPD-PWM•VPFC/Lp, where VPFC is the output voltage of PFC and Lp is the magnetized inductance of flyback transformer. Since the propagation delay is nearly constant, higher VPFC results in a larger additional current and the output power limit is higher than that of the low VPFC. To compensate for this variation, the peak current threshold is modulated by the RANGE output. When RANGE is shorted to GND, the PFC output voltage is higher and the corresponding threshold is 0.65V. When RANGE is opened, the PFC output voltage is lower and the corresponding threshold is 0.7V. Increasing the inductance of transformer improves this phenomenon. SG6841 Figure 13. Gate Drive Over-Current Protection (OCP) and ShortCircuit Protection (SCP) OCP and SCP are based on detection of feedback signal on FBPWM pin. Shown in Figure 14, if over-current or short-circuit occurs, FBPWM is pulled HIGH through the feedback loop. If the FB voltage is higher than 4.5V for longer than 56ms debounce time, SG6902 is turned off. Once VDD is lower than the turn-off threshold voltage, such as 10V, SG6902 is UVLO (under-voltage lockout) shut down. By the startup resistor, VDD is charged (up to the turn-on threshold voltage 16V) until SG6902 is enabled again. If the overloading condition still exists, the protection takes place repeatedly. This prevents the power supply from being overheated in overloading condition. The 650ms time-out signal prevents SG6902 from being latched off when the input voltage is fast on/off. © 2007 Fairchild Semiconductor Corporation Rev. 1.2.1 • 5/1/08 www.fairchildsemi.com 8 AN-6902 APPLICATION NOTE Figure 14. Over-Current Protection or Short-Circuit Protection Over-Temperature Protection (OTP) SG6902 provides an OTP pin for over-temperature protection. A constant current is output from this pin. If RI is equal to 24kΩ, the magnitude of the constant current is 100µA. An external NTC thermistor must be connected from this pin to ground as shown in Figure 15. When the OTP voltage drops below 1.2V, SG6902 is disabled until OTP voltage exceeds 1.4V. Referring to the maximum duty cycle and minimum input voltage at full load, the transformer inductance can be calculated as: Dmax = n × (VO + Vf ) VIN. min + n × (VO + Vf ) (32) (33) LP = η × (VIN max × Dmax )2 2 × POUT × fS × Br where Br is how much percentage of the output power is into CCM in low line input voltage. Normally, the Br is set as 30% ~ 50%. VIN.min = 250V. iav i pk Δi p I sq Figure 15. Over-Temperature Protection Flyback Transformer Design The turn ratio n = Np/Ns, is an important parameter for a flyback power converter. It affects the maximum duty of the switching signal when the input voltage is in minimum value. It also influences the voltage stresses of the MOSFET and the secondary rectifier. Refer to Equations 30 and 31. If n increases, the voltage stress of the MOSFET increases; however, the voltage stress of the secondary rectifier decreases accordingly. VDS. max = VIN. max + n × (VO + Vf ) V x VAK. max = IN.ma + VO n d max 1-d max Figure 16. Primary Current Waveform (30) (31) Figure 16 shows the primary current waveform. Once the inductor LP is determined, the primary peak current Ipk and average current Iav, at the full load and low line input voltage, can be expressed as: IAV = η × VIN. max × Dmax PO (34) (35) where Vf is the forward voltage of output diode and VIN.max = 400V. © 2007 Fairchild Semiconductor Corporation Rev. 1.2.1 • 5/1/08 V ΔIP = IN. max × Dmax × TS LP www.fairchildsemi.com 9 AN-6902 APPLICATION NOTE IPK = ΔIP + IAV 2 (36) (37) ISQ = IPK − ΔIP From Faraday’s law, the turns of primary side can be expressed as: NP = LP × IPK × 108 Bmax × A e NP × (VDD + Vfa ) × (1 − Dmax ) VIN. max × Dmax Figure 17 shows a transformer winding structure, including primary winding (Np1), copper layer (shield), secondary winding (Ns), auxiliary winding (AUX), copper layer (shield), and primary winding (Np2). Because the auxiliary winding is between secondary winding and shield windings, it can alleviate the variation of VDD voltage and avoid the VDD voltage reaching the over-voltage threshold of 24.5V for normal operation. (38) The turns of auxiliary winding can be expressed as: Naux = (39) where VDD is set to around 12V and Vfa is the forward voltage of VDD rectifier diode. Transformer Winding Structure The auxiliary winding of the transformer is developed to provide a power source (VDD voltage) to the control circuit. To produce a regulated VDD voltage, the reflected voltage of the auxiliary winding is designed to correlate to the output voltage of secondary winding. A switching voltage spike, caused by the leakage inductance of the primary winding, would be coupled to the auxiliary winding to increase the VDD voltage in response to the increase of the load. When the VDD voltage is increased higher than the voltage of the over-voltage protection 24.5V, the control circuit turns off the PWM and PFC stages to protect the power supply. Therefore, the transformer windings should prevent the auxiliary winding from primary winding interference. Figure 17. Winding Structure Lab Note Before rework or solder/desolder on the power supply, discharge primary capacitors by external bleeding resistor. Otherwise, the PWM IC may be destroyed by external high voltage during solder/desolder. This device is sensitive to ESD discharge. To improve production yield, the production line should be ESD protected according to ANSI ESD S1.1, ESD S1.4, ESD S7.1, ESD STM 12.1, and EOS/ESD S6.1 © 2007 Fairchild Semiconductor Corporation Rev. 1.2.1 • 5/1/08 www.fairchildsemi.com 10 AN-6902 APPLICATION NOTE Printed Circuit Board Layout Note that SG6902 has two ground pins. Good highfrequency or RF layout practices should be followed. Avoid long PCB traces and component leads. Locate decoupling capacitors near the SG6902. A resistor (5 ~ 20Ω) is recommended, connected in series from the OPFC and OPWM to the gate of the MOSFET. Isolating the interference between the PFC and PWM stages is also important. Figure 18 shows an example of the PCB layout. The ground trace connected from the AGND pin of SG6902 to the decoupling capacitor, which should be low impedance and as short as possible. The ground trace 1 provides a signal ground. It should be connected directly to the decoupling capacitor VDD and/or to the AGND pin of the SG6902. The ground trace 2 shows that the AGND pins should connect to the PFC output capacitor CO independently. The ground trace 3 is independently tied from the PGND to the PFC output capacitor CO. The ground in the output capacitor CO is the major ground reference for power switching. To provide a good ground reference and reduce the switching noise of both the PFC and PWM stages, the ground traces 6 and 7 should be located very near and be low impedance. The IPFC pin is connected directly to RS through R3 to improve noise immunity (beware that it may incorrectly be connected to the ground trace 2). The IMP and ISENSE pins should also be connected directly via the resistors R2 and RP to another terminal of RS. Due to the ground trace 4 and 5 is PFC and PWM stages Current loop, which should be as short as possible. Figure 18. PCB Layout © 2007 Fairchild Semiconductor Corporation Rev. 1.2.1 • 5/1/08 www.fairchildsemi.com 11 AN-6902 APPLICATION NOTE Related Datasheets SG6902 — Green Mode PFC / Flyback PWM Controller SG6901A — Green Mode PFC / Flyback PWM Controller DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2007 Fairchild Semiconductor Corporation Rev. 1.2.1 • 5/1/08 www.fairchildsemi.com 12