SG6902SZ

Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 The patented interleave-switching feature synchronizes the PFC and PWM stages and reduces switching noise. At light loads, the switching frequency is continuously decreased to reduce power consumption. If output loading is further reduced, the PFC stage is turned off to further reduce power consumption. For PFC stage, the proprietary multi-vector control scheme provides a fast transient response in a low-bandwidth PFC loop, in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, the SG6902 shuts off PFC to prevent extra-high voltage on output. Programmable two-level output voltage control reduces the PFC output voltage at low line input to increase the efficiency of the power supply. For the flyback PWM, the synchronized slope compensation ensures the stability of the current loop under continuous-conduction-mode operation. Built-in line-voltage compensation maintains a constant output power limit. Hiccup operation during output overloading is also guaranteed. In addition, SG6902 provides protection functions, such as brownout and RI pin open/short protections. FEATURES Green-mode PFC and PWM operation N o switching of PFC at light loads saves power Low start-up and operating current Innovative switching-charge multiplier-divider Multi-vector control for improved PFC output transient response Interleaved PFC/PWM switching P rogrammable two-level PFC output voltage A verage-current-mode control for PFC C ycle-by-cycle current limiting for PFC/PWM P FC over-voltage and under-voltage protections P FC and PWM feedback open-loop protection Brownout protection O ver-temperature protection APPLICATIONS S witching Power Supplies with Active PFC High-Power Adaptors DESCRIPTION The highly integrated SG6902 is designed for power supplies with boost PFC and Flyback PWM. It requires very few external components to achieve green-mode operation and versatile protections. It is available in a 20-pin SOP package. TYPICAL APPLICATION © System General Corp. Version 1.3.1 (IAO33.0022.B3) -1- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 MARKING DIAGRAM PIN CONFIGURATION SG6902TP XXXXXXXXYWWV T: S=SOP P : Z=Lead Free + ROHS Compatible Null=regular package XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location ORDERING INFORMATION Part Number SG6902SZ Pb-Free Package 20-pin SOP © System General Corp. Version 1.3.1 (IAO33.0022.B3) -2- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 PIN DESCIRPTIONS Name VRMS Pin No. 1 Type Line Voltage Detection Function Line voltage detection. The pin is used for PFC multiplier, RANGE control of PFC output voltage, and brownout protection. For brownout protection, the controller is disabled after a delay time when the VRMS voltage drops below a threshold. Reference setting. One resistor connected between RI and AGND determines the switching frequency. The switching frequency is equal to [1560 / RI] kHz, where RI is in kΩ. For example, if RI is 24kΩ, the switching frequency is 65kHz. RI 2 Oscillator Setting OTP 3 This pin supplies an over-temperature protection signal. A constant current is output from this pin. An external NTC thermistor must be connected from this pin to ground. Over-Temperature Protection The impedance of the NTC thermistor decreases whenever the temperature increases. Once the voltage of the OTP pin drops below the OTP threshold, the SG6902 is disabled. Output for PFC Current Amplifier Inverting Input for PFC Current Amplifier Non-Inverting Input for PFC Current Amplifier This is the output of the PFC current error amplifier. The signal from this pin is compared with an internal sawtooth and determines the pulse width for PFC gate drive. The inverting input of the PFC current error amplifier. Proper external compensation circuits result in excellent input power factor via average-current-mode control. The non-inverting input of the PFC current amplifier and also the output of multiplier. Proper external compensation circuits will result in excellent input power factor via average-current-mode control. IEA 4 IPFC 5 IMP 6 ISENSE FBPWM 7 8 Peak Current Limit Setting for The peak-current setting for PFC. PFC PWM Feedback Input The control input for voltage-loop feedback of PWM stage. It is internally pulled high through a resistor. An external opto-coupler from secondary feedback circuit is usually connected to this pin. The current-sense input for the flyback PWM. Via a current sense resistor, this pin provides the control input for peak-current-mode control and cycle-by-cycle current limiting. Signal ground. During start-up, the SS pin charges an external capacitor with a 50µA (RI=24kΩ) constant-current source. The voltage on FBPWM is clamped by SS during start-up. In the event of a protection condition occurring and/or PWM being disabled, the SS pin quickly discharges. The totem-pole output drive for the flyback PWM MOSFET. This pin is internally clamped under 18V to protect the MOSFET. Power ground. The totem-pole output drive for the PFC MOSFET. This pin is internally clamped under 18V to protect the MOSFET. The power supply pin. Two-level output voltage setting for PFC. The PFC output voltage at low line can be reduced to improve efficiency. The RANGE pin is of high impedance while the VRMS voltage is lower than a threshold. The PFC stage over-voltage input. The comparator disables the PFC output driver if the voltage at this input exceeds a threshold. This pin can be connected to FBPFC or it can be connected to the PFC boost output through a divider network. The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin is connected to the PFC output through a divider network. IPWM AGND SS 9 10 11 PWM Current Sense Ground PWM Soft-Start OPWM GND OPFC VDD RANGE 12 13 14 15 16 PWM Gate Drive Ground PFC Gate Drive Supply PFC Output Voltage Control OVP 17 PFC Over-Voltage Input Voltage Feedback Input for PFC FBPFC 18 VEA 19 The error amplifier output for PFC voltage feedback loop. A compensation network Error Amplifier Output for (usually a capacitor) is connected between this pin and ground. A large capacitor PFC Voltage Feedback Loop value results in a narrow bandwidth and improves the power factor. Input AC Current Before start-up, this input is used to provide start-up current for VDD. For normal operation, this input is used to provide current reference for the multiplier. IAC 20 © System General Corp. Version 1.3.1 (IAO33.0022.B3) -3- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 BLOCK DIAGRAM © System General Corp. Version 1.3.1 (IAO33.0022.B3) -4- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 ABSOLUTE MAXIMUM RATINGS Symbol VDD IAC VHIGH VLOW PD TJ TSTG RθJC TL ESD Parameter DC Supply Voltage* Input AC Current OPWM, OPFC, IAC Others Power Dissipation at TA < 50°C Operating Junction Temperature Storage Temperature Range Thermal Resistance (Junction-to-Case) Lead Temperature (Wave Soldering or Infrared, 10 Seconds) Electrostatic Discharge Capability, Human Body Model Electrostatic Discharge Capability y, Machine Model Value 25 2 -0.3 to +25.0 -0.3 to +7.0 SOP -40 to +125 -55 to +150 SOP 260 4.5 250 23.64 1.15 Unit V mA V V W °C °C °C/W °C KV V *All voltage values, except differential voltages, are given with respect to GND pin. *Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. RECOMMENDED OPERATING CONDITIONS Symbol TA Parameter Operating Ambient Temperature* Value -30 to +85 Unit °C *For proper operation. ELECTRICAL CHARACTERISTICS VDD=15V, TA=25°C unless otherwise noted. VDD Section Symbol VDD-OP IDD-ST IDD-OP VTH-ON VDD-MIN VDD-OVP TVDD-OVP VDD-TH-G Parameter Continuously Operating Voltage Start-up Current Operating Current Start Threshold Voltage Minimum Operating Voltage VDD OVP Threshold Debounce Time of VDD OVP VDD Low-Threshold Voltage to Exit Green-off Mode RI=24kΩ VTH-ON –0.16V OPFC, OPWM Open, RI=24kΩ 15 9 23.5 8 VDD-MIN +0.9 VDD-MIN +1.5 10 6 16 10 24.5 Test Conditions Min. Typ. Max. 20 25 10 17 11 25.5 25 VDD-MIN +2.1 Unit V µA mA V V V µs V © System General Corp. Version 1.3.1 (IAO33.0022.B3) -5- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 Oscillator & Green-Mode Operation Symbol VRI FOSC FOSC-MINFREQ RI RIOPEN RISHORT Parameter RI Voltage PWM Frequency Minimum Frequency in Green Mode RI Pin Resistance Range RI Pin Open Protection If RI> RIopen , SG6902 Turns Off RI Pin Short Protection If RI< RIshort , SG6902 Turns Off RI=24kΩ RI=24kΩ Test Conditions Min. 1.176 62 18.0 15 200 2 Typ. 1.200 65 20.0 Max. 1.224 68 22.5 47 Unit V KHz KHz KΩ KΩ KΩ VRMS for UVP and RANGE Symbol VRMS-UVP-1 VRMS-UVP-2 TD-PWM TUVP VRMS-H VRMS-L TRANGE VOL IOH Parameter RMS AC Voltage Under-Voltage Protection Threshold (with TUVP Delay) Recovery Level on VRMS When UVP Occurs, Interval from PFC Off to PWM Off Under-Voltage Protection Delay Time* High VRMS Threshold for RANGE Comparator Low VRMS Threshold for RANGE Comparator Range Enable Delay Time Output Low Voltage of RANGE Pin Output High Leakage Current of RANGE Pin RI=24kΩ Io=1mA RANGE=5V RI=24kΩ RI=24kΩ Test Conditions Min. 0.75 Typ. 0.80 Max. 0.85 Unit V VRMS-UVP-1 VRMS-UVP-1 VRMS-UVP-1 V +0.16V +0.18V +0.2V TUVP-Min+ 9 150 1.90 1.55 145 195 1.95 1.60 170 TUVP-Min+ ms 14 240 2.00 1.65 200 0.5 50 ms V V ms V nA * No delay for start-up. PFC STAGE Voltage Error Amplifier Symbol VREF Av-PFC* ZO* OVPPFC △OVPPFC TOVP-PFC VFBPFC-H GFBPFC-H* VFBPFC-L GFBPFC-L* IFBPFC-L IFBPFC-H UVPFBPFC VFBHIGH TUVP-PFC * Parameter Reference Voltage Open-Loop Gain Output Impedance PFC Over Voltage Protection (OVP Pin) PFC Feedback Voltage Protection Hysteresis Debounce Time of PFC OVP Clamp-High Feedback Voltage Clamp-High Gain Clamp-Low Feedback Voltage Clamp-Low Gain Maximum Source Current Maximum Sink Current PFC Feedback Under-Voltage Protection FB Open Voltage Debounce Time of PFC UVP Test Conditions Min. 2.95 Typ. 3.00 60 110 Max. 3.05 Unit V dB KΩ 3.20 60 RI=24kΩ 40 3.10 2.75 1.5 70 0.35 6 RI=24kΩ 40 3.25 90 70 3.15 0.5 2.85 6.5 2.0 110 0.40 7 70 3.30 120 120 3.20 2.90 V mV µs V mA/V V mA/mV mA µA 0.45 8 120 V V µs Not tested in production. © System General Corp. Version 1.3.1 (IAO33.0022.B3) -6- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 Current Error Amplifier Symbol VOFFSET AI*1 BW *1 CMRR*1 VOUT-HIGH VOUT-LOW IMR1, IMR2 IL IH Parameter Input Offset Voltage Open-Loop Gain Unit Gain Bandwidth Common Mode Rejection Ratio Output High Voltage Output Low Voltage Reference Current Source Maximum Source Current Maximum Sink Current RI=24kΩ (IMR=20+IRI•0.8) 50 3 0.25 VCM=0 to +1.5V 3.2 0.2 70 Test Conditions Min. Typ. 8 60 1.5 70 Max. Unit mV dB MHz dB V V µA mA mA Peak Current Limit Symbol IP VPK TPD-PFC TBNK-PFC Parameter Constant Current Output Peak Current Limit Threshold Voltage Cycle-by-Cycle Limit (VSENSE < VPK) Propagation Delay Leading-Edge Blanking Time 270 350 Test Conditions RI=24kΩ VRMS=1.05V VRMS=3V Min. 90 0.15 0.35 Typ. 100 0.20 0.40 Max. 110 0.25 0.45 200 450 Unit µA V V ns ns Multiplier Symbol IAC VDROP IMO–MAX*1 IMO-1 IMO–2 VIMP Parameter Input AC Current Voltage Drop from the IAC Pin to VDD Maximum Multiplier Current Output Multiplier Current Output (Low-line, High-power) Multiplier Current Output (High-line, High-power) Voltage of IMP Open Test Conditions Multiplier Linear Range IAC=240µA RI=24 kΩ VRMS=1.05V; IAC=90µA; VEA=7.5V; RI=24kΩ VRMS=3V; IAC=264µA; VEA=7.5V; RI=24kΩ 200 65 3.4 250 250 85 3.9 4.4 280 Min. 0 Typ. Max. 360 3.5 Unit µA V µA µA µA V PFC Output Driver Symbol VZ-PFC TPFC VOL-PFC VOH-PFC TR-PFC TF-PFC DCMAX-PFC Parameter Output Voltage Maximum (Clamp) Interval OPFC Lags Behind OPWM at Start-up Output Voltage Low Output Voltage High Rising Time Falling Time Maximum Duty Cycle Test Conditions VDD=20V RI=24kΩ VDD=15V; IO=100mA VDD=13V; IO=100mA VDD=15V; CL=5nF; OPFC=2V to 9V VDD=15V; CL=5nF; OPFC=9V to 2V 8 40 40 93 70 60 120 110 98 9.0 Min. Typ. 16 11.5 Max. 18 14.0 1.5 Unit V ms V V ns ns % © System General Corp. Version 1.3.1 (IAO33.0022.B3) -7- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 PWM STAGE FBPWM Symbol Av-PWM ZFB* IFB FBOPEN-LOOP TOPEN-PWM VPFC-OFF1 VPFC-OFF2 TPFC-OFF VPFC-ON 1.6 VPFC-ON 2.85 VPFC-ON 0.8 VPFC-ON 1.95 VN SG*1 VG * Parameter FB to Current Comparator Attenuation Input Impedance Maximum Source Current PWM Open-Loop Protection Threshold PWM Open-Loop Protection Delay Time PFC Off Voltage at FBPWM PFC Off Voltage at FBPWM PFC Off Delay Time PFC On Voltage at FBPWM PFC On Voltage at FBPWM PFC On Voltage at FBPWM PFC On Voltage at FBPWM Frequency Reduction Threshold on FBPWM Green-Mode Modulation Slope Voltage on FBPWM at FS=20KHz Test Conditions Min. 2.5 4 0.8 4.2 Typ. 3.1 5 1.2 4.5 56 VG+0.2V VG+0.2V Max. 3.5 7 1.5 4.8 70 Unit V/V KΩ mA V ms V V RI=24kΩ RANGE=Ground RANGE=Open RI=24kΩ RANGE=Ground VRMS=1.6V RANGE=Ground VRMS=2.85V RANGE=Open VRMS=0.8V RANGE=Open VRMS=1.95V RANGE=Ground 45 500 650 VG+0.35 V VG+0.35 V VG+0.85 V VG+0.5V 800 ms V V V V 1.9 60 1.35 2.1 75 1.60 2.3 90 1.75 V Hz/V V Not tested in production. PWM-Current Sense Symbol TPD-PWM VLIMIT-1 VLIMIT-2 TBNK-PWM △VSLOPE Parameter Propagation Delay to Output Peak Current Limit Threshold Voltage1 Peak Current Limit Threshold Voltage2 Leading-Edge Blanking Time Slope Compensation △VS=△VSLOPE x (Ton/T) △VS: Compensation Voltage Added to Current Sense RANGE=Open RANGE=Ground Test Conditions Min. 60 0.65 0.60 270 0.45 0.70 0.65 350 0.50 Typ. Max. 120 0.75 0.70 450 0.55 Unit ns V V ns V PWM Output Driver Symbol VZ-PWM VOL-PWM VOH-PWM TR-PWM TF-PWM DCMAX-PWM Parameter Output Voltage Maximum (Clamp) Output Voltage Low Output Voltage High Rising Time Falling Time Maximum Duty Cycle Test Conditions VDD=20V VDD=15V; IO=100mA VDD=13V; IO=100mA VDD=15V; CL=5nF; OPWM=2V to 9V VDD=15V; CL=5nF; OPWM=9V to 2V 8 30 30 73 60 50 78 120 110 83 Min. Typ. 16 Max. 18 1.5 Unit V V V ns ns % © System General Corp. Version 1.3.1 (IAO33.0022.B3) -8- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 OTP Section Symbol IOTP VOTP-OFF VOTP-ON TOTP Parameter OTP Pin Output Current OTP Threshold Voltage Recovery Level on OTP OTP Debounce Time RI=24kΩ Test Conditions RI=24kΩ Min. 90 1.15 1.35 8 Typ. 100 1.20 1.40 Max. 11 1.25 1.45 25 Unit µA V V µs Soft-Start Section Symbol ISS RD* * Parameter Constant Current Output for Soft-Start Discharge RDSON Test Conditions RI=24kΩ Min. 44 Typ. 50 470 Max. 56 Unit µA Ω Not tested in production. © System General Corp. Version 1.3.1 (IAO33.0022.B3) -9- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 TYPICAL CHARACTERISTICS Start-UP Current (IDD-ST) vs Temperature 11.0 10.8 10.6 10.4 VDD-MIN (V) 10.2 10.0 9.8 9.6 9.4 9.2 9.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Min. Operation Voltge (V DD-MIN) vs Temperature 20 18 16 14 IDD-ST (uA) 12 10 8 6 4 2 0 Temperature (℃) Temperature (℃) Start-up Current vs. VDD Voltage Frequency vs. FB Voltage 12 10 Start-up Current (uA) 8 6 4 2 0 0 1.65 3.3 4.95 6.6 8.25 9.9 11.55 13.2 14.85 16.5 18.15 70 60 Frequency (KHz) 50 40 30 20 10 0 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 VDD Voltage (V) FB Voltage (V) Start Threshold Voltage (VTH-ON) vs Temperature Duty cycle vs. FB Voltage 17.00 16.80 16.60 16.20 16.00 15.80 15.60 15.40 15.20 15.00 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 90 80 70 Duty cycle (%) 60 50 40 30 20 10 0 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 16.40 VTH-ON(V) Temperature (℃) FB Voltage (V) © System General Corp. Version 1.3.1 (IAO33.0022.B3) - 10 - www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 High VRMS Threshold for RANGE Comparator (V RMS-H ) vs Temperature 2.00 1.99 1.98 1.97 VRMS-H (V) 1.96 1.95 1.94 1.93 1.92 1.91 1.90 VDD OVP Threshold (VDD-OVP) vs Temperature 25.5 25.1 VDD-OVP (V) 24.7 24.3 23.9 23.5 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) Temperature (℃) PWM Frequency (FOSC) vs Temperature 68.0 67.5 67.0 66.5 66.0 65.5 65.0 64.5 64.0 63.5 63.0 62.5 62.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Low VRMS Threshold for RANGE Comarator (V RMS-L) vs Temperature 1.65 1.64 1.63 1.62 VRMS-L (V) 1.61 1.60 1.59 1.58 1.57 1.56 1.55 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ FOSC (KHz) Temperature (℃) Temperature (℃) PWM Frequency (FOSC-MINFREQ) vs Temperature Reference Voltage (V REF ) vs Temperature 3.05 3.04 3.03 3.02 VREF (V) 3.01 3.00 2.99 2.98 2.97 2.96 2.95 22.0 21.5 FOSC-MINFREQ (KHz) 21.0 20.5 20.0 19.5 19.0 18.5 18.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (℃) Temperature (℃) © System General Corp. Version 1.3.1 (IAO33.0022.B3) - 11 - www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 Maximum Duty Cycle (DCMAX) vs Temperature PFC over Voltage Protection (OVPPFC) vs Temperature 3.30 3.29 3.28 3.27 OVPPFC (V) 3.26 3.25 3.24 3.23 3.22 3.21 3.20 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 98.0 97.5 97.0 96.5 DCMAX (%) 96.0 95.5 95.0 94.5 94.0 93.5 93.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) Temperature (℃) Rising Time (T R) vs Temperature 120.0 110.0 100.0 90.0 T R (nS) 80.0 70.0 60.0 50.0 40.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ PWM Open Loop Protection voltage (FBOPEN-LOOP) vs Temperature 4.80 4.75 4.70 4.65 4.60 4.55 4.50 4.45 4.40 4.35 4.30 4.25 4.20 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ FBOPEN-LOOP (V) Temperature (℃) Temperature (℃) Falling Time (TF) vs Temperature PWM Open Loop Protection Delay Time (TOPEN-PWM) vs Temperature 110.0 100.0 TOPEN-PWM (mS) -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 75 72 69 66 63 60 57 54 51 48 45 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 90.0 TF (nS) 80.0 70.0 60.0 50.0 40.0 Temperature () Temperature (℃) © System General Corp. Version 1.3.1 (IAO33.0022.B3) - 12 - www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 Fall Time (TF-PWM ) vs Temperature 110.0 100.0 90.0 TF-PWM (nS) 80.0 70.0 60.0 50.0 40.0 30.0 Peak Current Limit Threshold Voltge1 (V LIMIT-1) vs Temperature 0.75 0.74 0.73 0.72 VLIMIT-1 (V) 0.71 0.70 0.69 0.68 0.67 0.66 0.65 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) Temperature (℃) Peak Current Limit Threshold Voltage2 (V LIMIT-2) vs Temperature Maximum Duty Cycle (DCMAXPWM) vs Temperature 83.0 82.0 81.0 DC MAXPWM (%) 80.0 79.0 78.0 77.0 76.0 75.0 74.0 73.0 0.70 0.69 0.68 0.67 VLIMIT-2 (V) 0.66 0.65 0.64 0.63 0.62 0.61 0.60 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) Temperature (℃) Rising Time (T R-PWM) vs Temperature OTP Threshold Voltage (VOTP-OFF ) vs Temperature 1.25 1.24 1.23 1.22 VOTP-OFF (V) 1.21 1.20 1.19 1.18 1.17 1.16 1.15 120.0 110.0 100.0 TR-PWM (nS) 90.0 80.0 70.0 60.0 50.0 40.0 30.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) Temperature (℃) © System General Corp. Version 1.3.1 (IAO33.0022.B3) - 13 - www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 OPERATION DESCRIPTION The highly integrated SG6902 is designed for power supplies with boost PFC and flyback PWM. It requires very few external components to achieve green-mode operation and versatile protections / compensation. The patented interleave-switching feature synchronizes the PFC and PWM stages and reduces switching noise. At light loads, the switching frequency is continuously decreased to reduce power consumption. If output loading is reduced, the PFC stage is turned off to further reduce power consumption. The PFC function is implemented by average-current-mode control. The patented switching charge multiplier-divider provides a high-degree noise immunity for the PFC circuit. The proprietary multi-vector output voltage control scheme provides a fast transient response in a low-bandwidth PFC loop, in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, the SG6902 shuts off PFC to prevent extra-high voltage on output. Programmable two-level output voltage control reduces the PFC output voltage at low line input to increase the efficiency of the power supply. For the flyback PWM, the synchronized slope compensation ensures the stability of the current loop under continuous-mode operation. Built-in line-voltage compensation maintains constant output power limit. Hiccup operation during output overloading is also guaranteed. To prevent the power supply from drawing large current during start-up, the start-up for PFC stage is delayed 11.5ms after the operation of PWM stage. In addition, SG6902 provides complete protection functions, such as brownout, over-voltage, and RI pin open/short protections. supply VDD during start-up. Since SG6902 consumes less than 25µA start-up current, the value of RAC can be large to reduce power consumption. One 10µF capacitor should hold enough energy for successful start-up. After start-up, S1 switches so that the current IAC is the input for PFC multiplier. This helps reduce circuit complexity and power consumption. FIG.1 Start-up Circuit Switching Frequency and Current Sources The switching frequency can be programmed by resistor RI connected between RI and GND. The relationship is: FOSC = 1560 (kHz) ----------RI (kΩ ) (1) Start-up Figure 1 shows the start-up circuit of the SG6902. A resistor RAC is utilized to charge VDD capacitor through S1. The turn-on and turn-off thresholds are fixed internally at 16V/10V. During start-up, the hold-up capacitor must be charged to 16V through the start-up resistor to enable SG6902. The hold-up capacitor continues to supply VDD before the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 10V during this start-up process. This UVLO hysteresis window ensures that hold-up capacitor is adequate to © System General Corp. Version 1.3.1 (IAO33.0022.B3) - 14 - For example, a 24kΩ resistor for RI results in a 65kHz switching frequency. Accordingly, a constant current, IT, flows through RI: IT = 1.2V (mA) ---------------RI (kΩ ) (2) IT is used to generate internal current reference. www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 Line-Voltage Detection (VRMS) Figure 2 shows a resistive divider with low-pass filtering for line-voltage detection on the VRMS pin. The VRMS voltage is used for the PFC multiplier, brownout protection, and range control. For brownout protection, the SG6902 is disabled with 195ms delay time if the voltage VRMS drops below 0.8V. For PFC multiplier and range control, refer to the sections below for details. FIG.3 Range Control Two-Level Output Voltage Interleave Switching and Green-Mode Operation The SG6902 uses interleaved switching to synchronize the PFC and flyback stages, which reduces switching noise and spreads the EMI emissions. Figure 4 shows off-time, TOFF, inserted between the turn-off of the PFC gate drive and the turn-on of the PWM. The off-time TOFF is increased in response to the decreasing of the voltage level of FBPWM. Therefore, the PWM switching frequency is continuously decreased to reduce switching losses. To further reduce power losses under extra light-load conditions, the PFC stage is turned off with a 650ms delay time. FIG.2 Line-Voltage Detection Circuit PFC Output Voltage Control (RANGE) For a universal input (90VAC ~ 264VAC) power supplies applying active boost PFC and flyback as a second stage, the output voltage of PFC is usually designed around 250V at low line and 390V at high line. This is to improve efficiency at low-line input. In SG6902, the RANGE pin (open-drain structure) is used for the two-level output voltage setting. Figure 3 shows the RANGE output that programs the PFC output voltage. The RANGE output is shorted to ground if the VRMS voltage exceeds 1.95V while high impedance (open) and the VRMS voltage drops below 1.6V. The output voltages can be designed using below equations: Range = Open ⇒ VO = R A + RB × 3V RB FIG.4 Interleaved Switching Pattern R + (RB // R C ) Range = Ground ⇒ VO = A × 3V (RB // R C ) ---- (3) © System General Corp. Version 1.3.1 (IAO33.0022.B3) - 15 - www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 FIG.5 Average-Current-Mode Control Loop PFC Operation The purpose of a boost active power factor corrector (PFC) is to shape the input current of a power supply. The input current waveform and phase follow that of the input voltage. Average-current-mode control is utilized for continuous-current-mode operation for the PFC booster. With the innovative multi-vector control for voltage loop and switching charge multiplier-divider for current reference, excellent input power factor is achieved with good noise immunity and transient response. Figure 5 shows the total control loop for the average-current-mode control circuit of SG6902. The current source output from the switching charge multiplier-divider can be expressed as: According to Equation 5, the minimum value of R2 and maximum of RS can be determined, because IMO should not exceed the specified maximum value. There are different concerns in determining the value of the sense resistor RS. The value of RS should be small enough to reduce power consumption, but large enough to maintain the resolution. A current transformer (CT) can improve the efficiency of high-power converters. To achieve good power factor, the voltage for VRMS and VEA should be kept as DC as possible, according to Equation 4. Good RC filtering for VRMS and narrow bandwidth (lower than the line frequency) for voltage loop are suggested for better input current shaping. The transconductance error amplifier has output impedance ZO (>90kΩ) and a capacitor CEA (1µF ~ 10µF) that should be connected to ground (as shown in Figure 5). This establishes a dominant pole f1 for the voltage loop: IMO = K × IAC × VEA (µA) -----------VRMS 2 (4) IIMP, the current output from the IMP pin, is the summation of IMO and IMR1. IMR1 and IMR2 are identical fixed-current sources. R2 and R3 are also identical. They are used to pull high the operating point of the IMP and IPFC pins since the voltage across RS goes negative with respect to ground. The constant current sources IMR1 and IMR2 are typically 60µA. Through the differential amplification of the signal across RS, better noise immunity is achieved. The output of IEA is compared with an internal sawtooth and the pulse width for PFC is determined. Through the average current-mode control loop, the input current, IS, is proportional to IMO: f1 = 1 ---------------------2π × R 0 ×CEA (6) The average total input power can be expressed as: Pin = VIN(rms) × IIN(rms) ∝ VRMS × IMO ∝ VRMS × I AC × VEA VRMS 2 Vin × VEA R AC VRMS 2 ---------------- (7) ∝ VRMS × = 2× VEA R AC IMO × R 2 = IS × R S -------------------© System General Corp. Version 1.3.1 (IAO33.0022.B3) (5) VEA, the output of the voltage error amplifier, controls the total input power and the power delivered to the load. - 16 - www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification Green-Mode PFC / Flyback-PWM Controller SG6902 Cycle-by-Cycle Current Limiting SG6902 provides cycle-by-cycle current limiting for both PFC and PWM stages. Figure 7 shows the peak current limit for the PFC stage. The PFC gate drive is terminated once the voltage on the ISENSE pin goes below VPK. The voltage of VRMS determines the voltage of VPK. The relationship between VPK and VRMS is shown in Figure 7. The amplitude of the constant current, IP, is determined by the internal current reference, IT, according to the following equation: Multi-vector Error Amplifier The voltage-loop error amplifier is transconductance, which has high output impedance (> 90kΩ). A capacitor CEA (1µ ~ 10µF) connected from VEA to ground provides a dominant pole for the voltage loop. Although the PFC stage has a low bandwidth voltage loop for better input power factor, the innovative multi-vector error amplifier provides a fast transient response to clamp the overshoot and undershoot of the PFC output voltage. Figure 6 shows the block diagram of the multi-vector error amplifier. When the variation of the feedback voltage exceeds ±5% of the reference voltage, the transconductance error amplifier adjusts its output impedance to increase the loop response. If RA is opened, SG6902 shuts off immediately to prevent extra-high voltage on the output capacitor. IP = 2 × IT = 2 × 1.2V --------------------RI (8) The peak current of the IS is given by (VRMS