SG6932

Product Specification Green-Mode PFC / Forward PWM Controller SG6932 DESCRIPTION The highly integrated SG6932 is designed for power supplies with boost PFC and forward PWM. It requires very few external components to achieve green-mode operation and versatile protections / compensation. It is available in 16-pin DIP and SOP packages. The patented interleave-switching feature synchronizes the PFC and PWM stages and reduces switching noise. At light load, the switching frequency is continuously decreased to reduce power consumption. For PFC stage, the proprietary multi-vector control scheme provides a fast transient response in a low-bandwidth PFC loop, in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, SG6932 shuts off to prevent extra-high voltage on output. For the Forward PWM stage, the synchronized slope compensation ensures the stability of the current loop under continuous-conduction-mode operation. Hiccup operation during output overloading is guaranteed. The soft-start and programmable maximum duty cycle ensure safe operation. SG6932 provides complete protection functions, such as brownout protection and RI open/short latch off. FEATURES OVERVIEW Interleaved PFC / PWM switching Green-mode PFC and PWM operation Low operating current Innovative switching-charge multiplier-divider Multi-vector control for improved PFC output transient response Average-current-mode for input-current shaping PFC over-voltage and under-voltage protections PFC and PWM feedback open-loop protection Cycle-by-cycle current limiting for PFC/PWM Slope compensation for PWM Selectable PWM maximum duty cycle 50% and 65% Brownout protection Power-on sequence control and soft-start APPLICATIONS Switch-mode power supplies with active PFC Servo system power supplies PC-ATX power supplies TYPICAL APPLICATION © System General Corp. Version 1.1.1 (IAO33.0011.B2) -1- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification Green-Mode PFC / Forward PWM Controller SG6932 PIN CONFIGURATION MARKING DIAGRAMS T: D=DIP, S=SOP P : Z =Lead Free + ROHS Compatible XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location VRMS RI IEA IPFC IMP ISENSE FBPWM IPWM 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 IAC VEA FBPFC SS VDD OPFC GND OPWM SG6932TP XXXXXXXXYWWV ORDERING INFORMATION Part Number SG6932DZ SG6932SZ (Preliminary) Pb-Free Package 16-pin DIP 16-pin SOP © System General Corp. Version 1.1.1 (IAO33.0011.B2) -2- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification Green-Mode PFC / Forward PWM Controller SG6932 PIN DESCRIPTIONS Name VRMS Pin No. Type 1 Line-Voltage Detection Function Line voltage detection. The pin is used for PFC multiplier and brownout protection. Reference setting. One resistor connected between RI and ground determines the switching frequency. A resistor with resistance between 12k ~ 47kΩ is recommended. The switching frequency is equal to [1560 / RI] kHz, where RI is in kΩ. For example, if RI is 24kΩ, the switching frequency is 65kHz. RI 2 Oscillator Setting IEA IPFC 3 4 Output of PFC Current This is the output of the PFC current amplifier. The signal from this pin is compared with an Amplifier internal sawtooth and determines the pulse width for PFC gate drive. Inverting Input of PFC The inverting input of the PFC current amplifier. Proper external compensation circuits Current Amplifier result in excellent input power factor via average-current-mode control. Non-inverting Input of The non-inverting input of the PFC current amplifier and the output of the multiplier. Proper PFC Current Amplifier external compensation circuits result in excellent input power factor via average current and Output of mode control. Multiplier Peak Current Limit Setting for PFC The peak current limit setting for PFC. IMP 5 ISENSE 6 FBPWM 7 The control input for voltage-loop feedback of PWM stage. It is internally pulled high through PWM Feedback Input a 6.5kΩ resistance. Usually an external opto-coupler from secondary feedback circuit is connected to this pin. PWM Current Sense PWM Gate Drive Ground PFC Gate Drive Supply The current sense input for the PWM stage. Via a current sense resistor, this pin provides the control input for peak-current-mode control and cycle-by-cycle current limiting. The totem pole output drive for PWM MOSFET. This pin is internally clamped under 18V to protect the MOSFET. The power ground. The totem pole output drive for the PFC MOSFET. This pin is internally clamped under 18V to protect the MOSFET. The power supply pin. The threshold voltages for start-up and turn-off are 14V and 10V, respectively. The operating current is lower than 10mA. During start-up, the SS pin charges an external capacitor with a 50µA constant current source. The voltage on FBPWM is clamped by SS during start-up. In the event of a protection condition occurring and/or PWM being disabled, the SS pin is quickly discharged. The voltage of SS pin can be used to select 50% or 65% maximum duty cycle. The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin is connected to the PFC output through a divider network. IPWM OPWM GND OPFC VDD 8 9 10 11 12 SS 13 PWM Soft-Start FBPFC 14 Voltage Feedback Input for PFC VEA 15 Error Amplifier Output The error amplifier output for PFC voltage feedback loop. A compensation network (usually for PFC Voltage a capacitor) is connected between this pin and ground. A large capacitor value results in a Feedback Loop narrow bandwidth and improves the power factor. Input AC Current For normal operation, this input is used to provide current reference for the multiplier. The suggested maximum IAC is 360µA. IAC 16 © System General Corp. Version 1.1.1 (IAO33.0011.B2) -3- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification Green-Mode PFC / Forward PWM Controller SG6932 BLOCK DIAGRAM © System General Corp. Version 1.1.1 (IAO33.0011.B2) -4- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification Green-Mode PFC / Forward PWM Controller SG6932 ABSOLUTE MAXIMUM RATINGS Symbol VDD IAC VHigh VLow PD TJ Tstg RθjC TL ESD Parameter DC Supply Voltage* Input AC Current OPWM, OPFC, IAC Others Power Dissipation Operating Junction Temperature Storage Temperature Range Thermal resistance (Junction-to-Case) Lead Temperature (Wave soldering, 10 seconds) Electrostatic Discharge Capability, Human Body Model Electrostatic Discharge Capability, Machine Model Test Conditions Value 25 2 -0.5 to 25V At TA RIopen , PWM Turned Off RI Pin Short Protection If RI< RIshort , PWM Turned Off Test Conditions RI=24kΩ RI=24kΩ Min. 1.176 62 18 12 Typ. 1.200 65 20 Max. 1.224 68 22 47 Unit V KHz KHz kΩ kΩ kΩ 200 2 © System General Corp. Version 1.1.1 (IAO33.0011.B2) -5- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification Green-Mode PFC / Forward PWM Controller SG6932 VRMS for UVP and ON/OFF Symbol VRMS-UVP-1 Parameter RMS AC Voltage Under-Voltage Threshold to Turn Off PFC (with TUVP Delay) for UVP Mode1 Test Conditions Min. 0.75 Typ. 0.8 Max. 0.85 Unit V VRMS-UVP-2 Recovery Level on VRMS for UVP Under-Voltage Protection Propagation to VRMS-UVP-1+ VRMS-UVP-1+ VRMS-UVP-1+ 0.17V RI=24kΩ 150 0.19V 195 0.21V 240 V TUVP Turn Off PFC Delay Time (No Delay for Start-up) ms PFC Stage Voltage Error Amplifier Symbol VREF Av Zo OVPFBPFC Parameter Reference Voltage Open-Loop Gain Output Impedance PFC Over-voltage Protection PFC Feedback Voltage Protection Hysteresis Clamp-High Feedback Voltage Clamp-High Gain Clamp-Low Feedback Voltage Clamp-Low Gain Maximum Source Current Maximum Sink Current PFC Feedback Under-Voltage Protection Output High Voltage on VEA Voltage level on FBPFC to Enable OPWM During Start-up Debounce Time of PFC UVP Test Conditions Min. 2.95 Typ. 3.00 60 110 Max. 3.05 Unit V dB kΩ 3.20 60 3.10 2.75 1.5 70 0.35 6 2.6 40 3.25 90 3.15 0.5 2.85 6.5 2.0 110 0.40 7 2.7 70 3.30 120 3.20 2.90 V mV V mA/V V mA/mV mA µA △OVPFBPFC VFBPFC-H GFBPFC-H VFBPFC-L GFBPFC-L IFBPFC-L. IFBPFC-H. UVPVFB VFBHIGH VRD-FBPFC TUVP-PFC 0.45 8 2.8 120 V V V µs Current Error Amplifier Symbol VOFFSET AI BW CMRR VOUT-HIGH VOUT-LOW IMR1, IMR2 IL IH Parameter Input Offset Voltage ((-) > (+)) Open-loop Gain Unit Gain Bandwidth Common-mode Rejection Ratio Output High Voltage Output Low Voltage Reference Current Source Maximum Source Current Maximum Sink Current Test Conditions Min. Typ. 8 60 1.5 Max. Unit mV dB MHz dB V VCM=0 ~ 1.5V 3.2 70 0.2 V µA mA mA RI=24kΩ (IMR=20+IRI•0.8) 50 3 0.25 70 © System General Corp. Version 1.1.1 (IAO33.0011.B2) -6- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification Green-Mode PFC / Forward PWM Controller SG6932 Peak Current Limit Symbol IP Vpk TpkD Bnkt Parameter Constant Current Output Peak Current Limit Threshold Voltage Cycle-by-Cycle Limit (Vsense < Vpk) Propagation Delay Leading-Edge Blanking Time Test Conditions RI=24kΩ VRMS=1.05V VRMS=3V Min. 90 0.15 0.35 270 Typ. 100 0.20 0.40 350 Max. 110 0.25 0.45 200 450 Unit µA V V ns ns Multiplier Symbol IAC IMO–max IMO-1 IMO–2 VIMP Parameter Input AC Current Maximum Multiplier Current Output; Multiplier Current Output (Low-Line, High-Power) Multiplier Current Output (High-Line, High-Power) Voltage of IMP Open Test Conditions Multiplier Linear Range RI=24kΩ VRMS=1.05V; IAC=90µA; VEA=7.5V; RI=24kΩ VRMS=3V; IAC=264µA; VEA=7.5V; RI=24kΩ Min. 0 Typ. 230 Max. 360 Unit µA µA 200 65 3.4 230 85 3.9 280 µA µA 4.4 V PFC Output Driver Symbol VZ-PFC VOL-PFC VOH-PFC TR-PFC Tf-PFC DC(MAX) Parameter Output Voltage Maximum (Clamp) Output Voltage Low Output Voltage High Rising Time Falling Time Maximum Duty Cycle Test Conditions VDD=20V VDD=15V; IO=100mA VDD=13V; IO=100mA VDD=15V; CL=5nF; O/P=2V to 9V VDD=15V; CL=5nF; O/P=9V to 2V Min. Typ. 16 Max. 18 1.5 Unit V V V ns ns % 8 40 40 93 70 60 120 110 97 PWM Stage FBPWM Symbol AV ZFB FBOPEN-LOOP TOPEN-PWM-Hiccup TOPEN-PWM VN SG VG Parameter FB to Current Comparator Attenuation Input Impedance PWM Open-Loop Protection Voltage Interval of PWM Open-Loop Protection Reset PWM Open-Loop Protection Delay Time Frequency Reduction Threshold on FBPWM Green-Mode Modulation Slope Voltage on FBPWM for Minimum Green-Mode Frequency Test Conditions Min. 2.2 4 4.2 Typ. 2.7 5 4.5 600 95 2.1 75 1.60 Max. Unit 3.2 7 4.8 700 120 2.3 90 1.75 V/V kΩ V ms ms V Hz/mV V RI=24kΩ RI=24kΩ 500 80 1.9 60 1.35 © System General Corp. Version 1.1.1 (IAO33.0011.B2) -7- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification Green-Mode PFC / Forward PWM Controller SG6932 PWM-Current Sense Symbol TPD-PWM VLIMIT TBNK-PWM Parameter Propagation Delay to Output – VLIMIT Loop Peak Current Limit Threshold Voltage Leading-Edge Blanking Time Slope Compensation △Vs=△VSLOPE x (Ton/T) △Vs: Compensation Voltage Added to Current Sense Test Conditions VDD=15V, OPWM drops to 9V Min. 60 0.65 270 Typ. 0.70 350 Max. 120 0.75 450 Unit ns V ns △VSLOPE 0.40 0.45 0.55 V Output Driver Symbol VZ-PWM TPWM VOL-PWM VOH-PWM TR-PWM TF-PWM Parameter Output Voltage Maximum (Clamp) Interval of OPWM Lags Behind OPFC at Start-up Output Voltage Low Output Voltage High Rising Time Falling Time Test Conditions VDD=20V RI=24kΩ VDD=15V; IO=100mA VDD=13V; IO=100mA VDD=15V; CL=5nF; O/P=2V to 9V VDD=15V; CL=5nF; O/P=9V to 2V Min. 2 Typ. 16 4 Max. 18 6 1.5 Unit V ms V V ns ns 8 30 30 60 50 120 110 Maximum Duty Cycle Symbol DC SS=6V DC SS=5V Parameter Maximum Duty Cycle for SS=6V Maximum Duty Cycle for SS=5V Test Conditions RI=24kΩ RI=24kΩ Min. 62 46 Typ. Max. 66 50 Unit % % Soft-Start Symbol ISS VDC-MAX-50% VDC-MAX--65% RD Parameter Constant Current Output for Soft-Start Voltage of SS for 50% Maximum Duty Cycle Voltage of SS for 65% Maximum Duty Cycle Discharge Resistance Test Conditions RT=24kΩ Min. 44 6 Typ. 50 Max. 56 5 Unit µA V V Ω 470 © System General Corp. Version 1.1.1 (IAO33.0011.B2) -8- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification Green-Mode PFC / Forward PWM Controller SG6932 TYPICAL CHARACTERISTICS Start-Up Current (IDD ST) vs Temperature Min. Operation Voltge (VDD-MIN) vs Temperature 20.0 18.0 16.0 14.0 IDD ST (uA) 11.0 10.8 10.6 10.4 VTH-MIN(V) -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 12.0 10.0 8.0 6.0 4.0 2.0 0.0 Temperature (℃) 10.2 10.0 9.8 9.6 9.4 9.2 9.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature ( ℃) Start Threshold Voltage (VTH-ON) vs Temperature Frequency vs. FB Voltage 15.0 14.8 14.6 Frequency (KHz) 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 1.3 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 14.4 VTH-ON(V) 14.2 14.0 13.8 13.6 13.4 13.2 13.0 Temperature ( ℃) FB Voltage (V) Start-up Current vs. VDD Voltage Duty Cycle vs. FB Voltage 70.0 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 60.0 50.0 Duty Cycle (%) VDD Voltage (V) Start-up Current (uA) 40.0 30.0 20.0 10.0 0.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 FB Voltage (V) © System General Corp. Version 1.1.1 (IAO33.0011.B2) -9- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification Green-Mode PFC / Forward PWM Controller VDD OVP Threshold (VDD-OVP) vs Temperature SG6932 PFC over Voltage Protection (OVPPFC) vs Temperature 25.5 25.3 25.1 VDD-OVP (V) 3.30 3.29 3.28 3.27 OVPPFC (V) 24.9 24.7 24.5 24.3 24.1 23.9 23.7 23.5 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 3.26 3.25 3.24 3.23 3.22 3.21 3.20 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature ( ℃) Temperature ( ℃) PWM Frequency (FOSC) vs Temperature Rising Time (TR-PFC) vs Temperature 68.0 67.5 67.0 66.5 66.0 65.5 65.0 64.5 64.0 63.5 63.0 62.5 62.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature ( ℃) 100.0 90.0 80.0 TR(nS) FOSC (KHz ) 70.0 60.0 50.0 40.0 30.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) PWM Frequency (FOSC-GREEN) vs Temperature F alling Time (TF-PFC) vs Temperature 22.0 21.5 FOSC-MINFREQ (KHz) 100.0 90.0 80.0 TF (nS) -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 21.0 20.5 20.0 19.5 19.0 18.5 18.0 Temperature ( ℃) 70.0 60.0 50.0 40.0 30.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) Reference Voltage (VREF) vs Temperature Maximum Duty Cycle (SS=5V) vs Temperature 3.05 3.04 3.03 3.02 DCMAX (%) -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 50.0 49.5 49.0 48.5 48.0 47.5 47.0 46.5 46.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ VREF (V) 3.01 3.00 2.99 2.98 2.97 2.96 2.95 Temperature ( ℃) Temperature ( ℃) © System General Corp. Version 1.1.1 (IAO33.0011.B2) - 10 - www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification Green-Mode PFC / Forward PWM Controller Maximum Duty Cycle (SS=6V) vs Temperature SG6932 Rising Time (TR-PWM) vs Temperature 66.0 65.5 65.0 DCMAX (%) 120.0 110.0 100.0 TR-PWM (nS) -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 64.5 64.0 63.5 63.0 62.5 62.0 Temperature ( ℃) 90.0 80.0 70.0 60.0 50.0 40.0 30.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) PWM Open Loop Protection voltage (FBOPEN-LOOP) vs Temperature Fall Time (TF-PWM) vs Temperature 4.80 4.75 4.70 4.65 4.60 4.55 4.50 4.45 4.40 4.35 4.30 4.25 4.20 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 110.0 100.0 90.0 TF-PWM (nS) FBOPEN-LOOP (V) 80.0 70.0 60.0 50.0 40.0 30.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) Temperature (℃) PWM Open Loop Protection Delay Time (TOPEN-PWM) vs Temperature Constant Current Output for Soft Start (ISS) vs Temperature 120 115 TOPEN-PWM (mS) 55 54 53 52 ISS (uA) -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 110 105 100 95 90 85 80 Temperature ( ℃) 51 50 49 48 47 46 45 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature ( ℃) Peak Current Limit Threshold Voltge (VLIMIT) vs Temperature 0.75 0.74 0.73 0.72 VLIMIT (V) 0.71 0.70 0.69 0.68 0.67 0.66 0.65 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature ( ℃) © System General Corp. Version 1.1.1 (IAO33.0011.B2) - 11 - www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification Green-Mode PFC / Forward PWM Controller SG6932 OPERATION DESCRIPTION The highly integrated SG6932 is designed for power supplies with boost PFC and forward PWM. It requires very few external components to achieve green-mode operation and versatile protections / compensation. The patented interleave-switching feature synchronizes the PFC and PWM stages and reduces switching noise. At light load, the switching frequency is linearly decreased to reduce power consumption. The PFC function is implemented by averagecurrent-mode control. The patented switching charge multiplier-divider provides high-degree noise immunity for the PFC circuit. This also enables the PFC circuit to operate over a much wider region. The proprietary multi-vector output voltage control scheme provides a fast transient response in a low-bandwidth PFC loop, in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, the SG6932 shuts off PFC to prevent extra-high voltage on output. For the forward PWM, the synchronized slope compensation ensures the stability of the current loop under continuous-mode operation. Hiccup operation during output overloading is also guaranteed. To prevent the power supply from drawing large current during start-up, the start-up for PWM stage is delayed 4ms after the PFC output voltage reaches its setting value. In addition, SG6932 provides complete protection functions such as brownout protection and built-in latch for over-voltage and RI open/short. Figure 1. Input Voltage Detection Switching Frequency / Current Sources The switching frequency of SG6932 can be programmed by the resistor RI connected between RI pin and GND. The relationship is: fPWM = 1560 ( kHz ) ------------RI (kΩ) (1) For example, a 24kΩ resistor RI results in a 65kHz switching frequency. Accordingly, constant current IT flows through RI. I T = 1.2V RI (kΩ ) ( mA) ---------------- (2) IT is used to generate internal current reference. IAC signal Figure 1 shows the IAC pin connected to input voltage by a resistance and the current, IAC, is the input for PFC multiplier. For the linear range of IAC 0~360µA, the range input voltage should be connected a resistance over 1.2M. Line Voltage Detection (VRMS) Figure 2 shows a resistive divider with low-pass filtering for line-voltage detection on VRMS pin. The VRMS voltage is used for the PFC multiplier and brownout protection. For brownout protection, when the VRMS voltage drops below 0.8V, OPFC turns off. © System General Corp. Version 1.1.1 (IAO33.0011.B2) - 12 - www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification Green-Mode PFC / Forward PWM Controller SG6932 Figure 4. Control Loop of PFC Stage Figure 2. Line-Voltage Detection on VRMS Pin The current source output from the switching charge multiplier-divider can be expressed as: Interleave Switching / Green-Mode The SG6932 uses interleaved switching to synchronize the PFC and PWM stages. This reduces switching noise and spreads the EMI emissions. Figure 3 shows off-time (TOFF) inserted between the turn-off of the PFC gate drives and the turn-on of the PWM. The off-time (TOFF) is increased in response to the decreasing of the voltage level of FBPWM; therefore, the PWM switching frequency is linearly decreased to reduce switching losses. IMO = K × IAC × VEA (µA ) VRMS 2 (3) IMP, the current output from IMP pin, is the summation of IMO and IMR1. IMR1 and IMR2 are identical fixed-current sources. R2 and R3 are also identical. They are used to pull high the operating point of the IMP and IPFC pins when the voltage across RS goes negative with respect to ground. Through the differential amplification of the signal across RS, better noise immunity is achieved. The output of IEA is compared with an internal sawtooth and the pulse width for PFC is determined. Through the average current-mode control loop, the input current IS is proportional to IMO: OPFC OPWM TOFF IMO × R 2 = IS × RS (4) Figure 3. Interleaved Switching According to Equation 4, the minimum value of R2 and maximum of RS can be determined since IMO should not exceed the specified maximum value. There are different concerns in determining the value of the sense resistor, RS. The value of RS should be small enough to reduce power consumption, but large enough to maintain the resolution. A current transformer (CT) may be used to improve the efficiency of high power converters. To achieve good power factor, the voltage for VRMS and VEA should be kept as DC as possible, according to Equation 3. Good RC filtering for VRMS and narrow bandwidth (lower than the line frequency) for voltage loop are suggested for better input current shaping. The www.sg.com.tw • www.fairchildsemi.com September 19, 2007 PFC Operation The purpose of a boost active power factor corrector (PFC) is to shape the input current of a power supply. The input current waveform and phase follow that of the input voltage. Using SG6932, average-current-mode control is utilized for continuous-current-mode operation for the PFC booster. With the innovative multi-vector control for voltage loop and switching-charge multiplier-divider for current reference, excellent input power factor is achieved with good noise immunity and transient response. Figure 4 shows the total control loop for the average-current-mode control circuit of SG6932. © System General Corp. Version 1.1.1 (IAO33.0011.B2) - 13 - Product Specification Green-Mode PFC / Forward PWM Controller transconductance error amplifier has output impedance RO (>90kΩ) and a capacitor CEA (1µF ~ 10µF) connected to ground (as shown in Figure 5). This establishes a dominant pole f1 for the voltage loop: SG6932 3.15V + SG69XX f1 = 1 2π × R0 × CEA 2.85V (5) RA FBPFC 3V The average total input power can be expressed as: + RB K IACxVEA V RMS 2 Pin = Vin( rms ) × Iin( rms ) ∝ VRMS × I MO ∝ VRMS × I AC × VEA 2 VRMS C EA VEA (6) Figure 5. Multi-Vector Error Amplifier Vin × VEA RAC ∝ VRMS × ∝ VEA 2 VRMS From Equation 6, VEA, the output of the voltage error amplifier, actually controls the total input power and the power delivered to the load. Cycle-by-Cycle Current Limiting SG6932 provides cycle-by-cycle current limiting for both PFC and PWM stages. Figure 6 shows the peak current limit for the PFC stage. The PFC gate drive is terminated once the voltage on the ISENSE pin goes below VPK. The voltage of VRMS determines the voltage of VPK. The relationship between VPK and VRMS is shown in Figure 6. The amplitude of the constant current, IP, is determined by the internal current reference, IT, according to the equation: Multi-Vector Error Amplifier The voltage-loop error amplifier is transconductance, which has high output impedance (> 90kΩ). A capacitor CEA (1µF ~ 10µF) connected from VEA to ground provides a dominant pole for the voltage loop. Although the PFC stage has a low bandwidth voltage loop for better input power factor, the innovative multi-vector error amplifier provides a fast transient response to clamp the overshoot and undershoot of the PFC output voltage. Figure 5 shows the block diagram of the multi-vector error amplifier. When the variation of the feedback voltage exceeds ± 5% of the reference voltage, the transconductance error amplifier adjusts its output impedance to increase the loop response. If RA is opened, SG6932 shuts off immediately to prevent extra-high voltage on the output capacitor. Ip = 2 × I T = 2× 1.2V R I (7) Therefore, the peak current of the IS is given by (VRMS