SI3442

March 2001 SI3442DV N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMICA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. Features 4.1 A, 20 V. RDS(ON) = 0.06 Ω @ VGS = 4.5 V RDS(ON) = 0.075 Ω @ VGS =2.7 V. Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. ____________________________________________________________________________________________ 4 3 5 2 6 1 Absolute Maximum Ratings T A = 25°C unless otherwise note Symbol Parameter VDSS VGSS ID PD Drain-Source Voltage Gate-Source Voltage - Continuous Drain Current - Continuous - Pulsed Maximum Power Dissipation (Note 1a) (Note 1b) (Note 1c) (Note 1a) SI3442DV 20 8 4.1 15 1.6 1 0.8 -55 to 150 °C W V V A TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 78 30 °C/W °C/W © 2001Fairchild Semiconductor Corporation SI3442DV Rev. A ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS IGSSF IGSSR VGS(th) RDS(ON) Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA VDS = 16 V, VGS = 0 V TJ = 55oC Gate - Body Leakage, Forward Gate - Body Leakage, Reverse VGS = 8 V, VDS = 0 V VGS = -8 V, VDS= 0 V VDS = VGS, ID = 250 µA TJ = 125oC Static Drain-Source On-Resistance VGS = 4.5 V, ID = 4.1 A TJ = 125oC VGS = 2.7 V, ID = 3.6 A ID(on) gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd On-State Drain Current Forward Transconductance VGS = 4.5 V, VDS = 5 V VDS = 4.5 V, ID = 4.1 A VDS = 10 V, VGS = 0 V, f = 1.0 MHz 15 12 0.4 0.3 0.7 0.5 0.039 0.06 0.05 20 1 10 100 -100 V µA µA nA nA ON CHARACTERISTICS (Note 2) Gate Threshold Voltage 1 0.8 0.06 0.11 0.075 A S V Ω DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance 365 230 95 pF pF pF SWITCHING CHARACTERISTICS (Note 2) Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 10 V, ID = 4.1 A, VGS = 4.5 V VDD = 5 V, ID = 1 A, VGEN = 4.5 V, RGEN = 6 Ω 9 25 28 8 10 1 3.3 17 45 50 15 14 ns ns ns ns nC nC nC SI3442DV Rev.A ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS IS VSD Continuous Source Diode Current Drain-Source Diode Forward Voltage Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. 1.3 VGS = 0 V, IS = 1.3 A (Note 2) 0.75 1.2 A V PD( t) = R θJ At ) ( T J−TA = R θJ C RθCA t ) + ( T J−TA = I 2 (t ) × RDS (ON ) D TJ Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 78oC/W when mounted on a 1 in2 pad of 2oz copper. b. 125oC/W when mounted on a 0.01 in2 pad of 2oz copper. c. 156oC/W when mounted on a 0.003 in2 pad of 2oz copper. 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. SI3442DV Rev.A Typical Electrical Characteristics 15 , DRAIN-SOURCE CURRENT (A) 2.5 R DS(on) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE 12 VGS = 4.5V 3.0V 2.7V 2.5V 2 2.0V 9 VGS =2.0V 1.5 2.5V 6 2.7V 3.0V 3.5V 3 1.5V 1 4.5V I D 0 0 V DS 0.5 1 2 3 , DRAIN-SOURCE VOLTAGE (V) 0 3 I D 6 9 12 15 , DRAIN CURRENT (A) Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.8 DRAIN-SOURCE ON-RESISTANCE DRAIN-SOURCE ON-RESISTANCE 2.5 I D = 4.1A 1.6 1.4 1.2 1 0.8 0.6 -50 RDS(ON) , NORMALIZED V GS = 4.5V R DS(on) , NORMALIZED VGS = 4.5V 2 T = 125°C J 1.5 25°C 1 0.5 -55°C -25 0 J 25 50 75 100 125 150 0 0 3 6 9 12 15 T , JUNCTION TEMPERATURE (°C) I D, DRAIN CURRENT (A) Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Drain Current and Temperature. 15 GATE-SOURCE THRESHOLD VOLTAGE 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 -50 -25 0 J V DS =- 5V I , DRAIN CURRENT (A) 12 25°C TJ = -55°C 125°C Vth , NORMALIZED VDS = VGS I D = 250µA 9 6 D 3 0 0 0.5 V GS 1 1.5 2 2.5 3 25 50 75 100 125 150 , GATE TO SOURCE VOLTAGE (V) T , JUNCTION TEMPERATURE (°C) Figure 5. Transfer Characteristics. Figure 6. Gate Threshold Variation with Temperature. SI3442DV Rev.A Typical Electrical Characteristics (continued) DRAIN-SOURCE BREAKDOWN VOLTAGE 1.12 I S , REVERSE DRAIN CURRENT (A) 10 5 1 ID = 250µA 1.08 VGS =0V TJ = 125°C BV DSS , NORMALIZED 1.04 0.1 25°C -55°C 1 0.01 0.96 0.001 0.92 -50 -25 T 0 J 25 50 75 100 125 150 0.0001 0 0.2 0.4 0.6 0.8 1 1.2 , JUNCTION TEMPERATURE (°C) VSD , BODY DIODE FORWARD VOLTAGE (V) Figure 7. Breakdown Voltage Variation with Temperature. Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature. 1500 1000 CAPACITANCE (pF) 600 5 VGS , GATE-SOURCE VOLTAGE (V) VDS = 5V I D = 4.1A 10V 15V 4 Ciss 300 200 3 Coss f = 1 MHz V GS = 0V 2 100 Crss 1 50 0.1 0 0.2 V DS 0.5 1 2 5 10 20 0 3 6 Q g , GATE CHARGE (nC) 9 12 , DRAIN TO SOURCE VOLTAGE (V) Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristics. VDD t d(on) t on t off tr 90% t d(off) 90% tf V IN D RL V OUT VOUT 10% VGS R GEN 10% INVERTED G DUT 90% S V IN 10% 50% 50% PULSE WIDTH Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. SI3442DV Rev.A Typical Electrical and Thermal Characteristics (continued) gFS , TRANSCONDUCTANCE (SIEMENS) 25 STEADY-STATE POWER DISSIPATION (W) 2 VDS = 5V 20 1a T = -55°C J 25°C 125°C 1.5 15 1 1b 1c 10 0.5 4.5"x5" FR-4 Board TA = 2 5 C Still Air o 5 0 0 2 4 6 8 10 ID , DRAIN CURRENT (A) 0 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 Figure 13. Transconductance Variation with Drain Current and Temperature. Figure 14. SuperSOTTM-6 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. I D, STEADY-STATE DRAIN CURRENT (A) 5 20 10 I D, DRAIN CURRENT (A) 1a 4.5 4 5 2 1 0.5 0.2 0.1 0.05 0.02 RD S(O N) LIM IT 100 1m s 10m s 100 ms 1s us 3.5 1b 1c 3 2.5 2 0 0.2 0.4 0.6 4.5"x5" FR-4 Board TA = 25 oC Still Air VGS = 4.5V VGS = 4.5V SINGLE PULSE R JA = See Note 1c θ TA = 25°C DC 0.8 2 1 2oz COPPER MOUNTING PAD AREA (in ) 0.01 0.1 0.2 0.5 V DS 1 2 5 10 20 40 , DRAIN-SOURCE VOLTAGE (V) Figure 15. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. Figure 16. Maximum Safe Operating Area. 1 TRANSIENT THERMAL RESISTANCE 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.00001 0.0001 0.001 0.01 0.1 t 1 , TIME (sec) 1 10 100 300 D = 0 .5 r(t), NORMALIZED EFFECTIVE 0 .2 0 .1 0 .05 0 .02 0 .01 S ingle Pulse P(pk) R θJA (t) = r(t) * R θJA R JA = See Note 1c θ t1 TJ - T A t2 =P *R (t) θJA D uty Cycle, D = t 1 / t 2 Figure 17. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. SI3442DV Rev.A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ DISCLAIMER FAST  FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ PowerTrench  QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER  SMART START™ Star* Power™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ UltraFET  VCX™ FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H1