SSS7N60B

SSP7N60B/SSS7N60B SSP7N60B/SSS7N60B 600V N-Channel MOSFET General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supplies. Features • • • • • • • 7.0A, 600V, RDS(on) = 1.2Ω @VGS = 10 V Low gate charge ( typical 38 nC) Low Crss ( typical 23 pF) Fast switching 100% avalanche tested Improved dv/dt capability TO-220F package isolation = 4.0kV (Note 6) D G GDS TO-220 SSP Series GD S TO-220F SSS Series S Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TJ, TSTG TL TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) Drain Current - Pulsed (Note 1) SSP7N60B 600 7.0 4.4 28 ± 30 (Note 2) (Note 1) (Note 1) (Note 3) SSS7N60B 7.0 * 4.4 * 28 * 420 7.0 14.7 5.5 Units V A A A V mJ A mJ V/ns W W/°C °C °C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TC = 25°C) - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds 147 1.18 -55 to +150 300 48 0.38 * Drain current limited by maximum junction temperature Thermal Characteristics Symbol RθJC RθCS RθJA Parameter Thermal Resistance, Junction-to-Case Max. Thermal Resistance, Case-to-Sink Typ. Thermal Resistance, Junction-to-Ambient Max. SSP7N60B 0.85 0.5 62.5 SSS7N60B 2.6 -62.5 Units °C/W °C/W °C/W ©2002 Fairchild Semiconductor Corporation Rev. B, June 2002 SSP7N60B/SSS7N60B Electrical Characteristics Symbol Parameter TC = 25°C unless otherwise noted Test Conditions Min Typ Max Units Off Characteristics BVDSS ∆BVDSS / ∆TJ IDSS IGSSF IGSSR Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse VGS = 0 V, ID = 250 µA ID = 250 µA, Referenced to 25°C VDS = 600 V, VGS = 0 V VDS = 480 V, TC = 125°C VGS = 30 V, VDS = 0 V VGS = -30 V, VDS = 0 V 600 ------0.65 ------10 100 100 -100 V V/°C µA µA nA nA On Characteristics VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, ID = 250 µA VGS = 10 V, ID = 3.5 A VDS = 40 V, ID = 3.5 A (Note 4) 2.0 --- -1.0 8.2 4.0 1.2 -- V Ω S Dynamic Characteristics Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz ---1380 115 23 1800 150 30 pF pF pF Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 480 V, ID = 7.0 A, VGS = 10 V (Note 4, 5) VDD = 300 V, ID = 7.0 A, RG = 25 Ω (Note 4, 5) -------- 30 80 125 85 38 6.4 15 70 170 260 180 50 --- ns ns ns ns nC nC nC Drain-Source Diode Characteristics and Maximum Ratings IS ISM VSD trr Qrr Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 7.0 A Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS = 0 V, IS = 7.0 A, dIF / dt = 100 A/µs (Note 4) ------ ---415 4.6 7.0 28 1.4 --- A A V ns µC Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 15.7mH, IAS = 7.0A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C 3. ISD ≤ 7.0A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2% 5. Essentially independent of operating temperature 6. Only for back side in Viso = 4.0kV and t = 0.3s ©2002 Fairchild Semiconductor Corporation Rev. B, June 2002 SSP7N60B/SSS7N60B Typical Characteristics 10 1 ID, Drain Current [A] ID, Drain Current [A] VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V 5.5 V Bottom : 5.0 V Top : 10 1 150 C 10 0 o 10 0 25 C -55 C o o 10 -1 ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ ※ Notes : 1. VDS = 40V 2. 250μ s Pulse Test 10 10 -1 -1 10 0 10 1 2 4 6 8 10 VDS, Drain-Source Voltage [V] VGS, Gate-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 5 4 10 1 RDS(ON) [Ω ], Drain-Source On-Resistance 3 VGS = 20V IDR, Reverse Drain Current [A] VGS = 10V 2 10 0 150℃ 25℃ ※ Notes : 1. VGS = 0V 2. 250μ s Pulse Test 1 ※ Note : TJ = 25℃ 0 0 5 10 15 20 25 10 -1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ID, Drain Current [A] VSD, Source-Drain voltage [V] Figure 3. On-Resistance Variation vs Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation with Source Current and Temperature 3000 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 12 2500 10 VDS = 120V VDS = 300V 2000 VGS, Gate-Source Voltage [V] 8 Capacitance [pF] Ciss 1500 VDS = 480V 6 1000 Coss Crss ※ Notes : 1. VGS = 0 V 2. f = 1 MHz 4 500 2 ※ Note : ID = 7.0 A 0 -1 10 0 10 0 10 1 0 5 10 15 20 25 30 35 40 VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC] Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics ©2002 Fairchild Semiconductor Corporation Rev. B, June 2002 SSP7N60B/SSS7N60B Typical Characteristics (Continued) 1.2 3.0 2.5 BV DSS , (Normalized) Drain-Source Breakdown Voltage RDS(ON) , (Normalized) Drain-Source On-Resistance 1.1 2.0 1.0 1.5 1.0 0.9 ※ Notes : 1. VGS = 0 V 2. ID = 250 μ A 0.5 ※ Notes : 1. VGS = 10 V 2. ID = 3.5 A 0.8 -100 -50 0 50 100 o 150 200 0.0 -100 -50 0 50 100 o 150 200 TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs Temperature Figure 8. On-Resistance Variation 10 10 2 2 Operation in This Area is Limited by R DS(on) Operation in This Area is Limited by R DS(on) 10 1 10 100 µs µs 10 ms DC 10 1 100 µs 1 ms 10 ms 100 ms ID, Drain Current [A] ID, Drain Current [A] 1 ms 10 0 10 0 DC 10 -1 ※ Notes : 1. TC = 25 C o 2. TJ = 150 C 3. Single Pulse o 10 -1 ※ Notes : 1. TC = 25 C o 2. TJ = 150 C 3. Single Pulse o 10 -2 10 0 -2 10 10 1 10 2 10 3 10 0 10 1 10 2 10 3 VDS, Drain-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 9-1. Maximum Safe Operating Area for SSP7N60B Figure 9-2. Maximum Safe Operating Area for SSS7N60B 8 6 ID, Drain Current [A] 4 2 0 25 50 75 100 125 150 TC, Case Temperature [℃] Figure 10. Maximum Drain Current vs Case Temperature ©2002 Fairchild Semiconductor Corporation Rev. B, June 2002 SSP7N60B/SSS7N60B Typical Characteristics (Continued) (t), T h e r m a l R e s p o n s e 10 0 D = 0 .5 0 .2 10 -1 ※ N o te s : 1 . Z θ J C (t) = 0 .8 5 ℃ /W M a x . 2 . D u ty F a c to r, D = t 1 /t 2 3 . T J M - T C = P D M * Z θ J C (t) 0 .1 0 .0 5 0 .0 2 0 .0 1 s in g le p u ls e PDM t1 t2 Z θ JC 10 -2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ] Figure 11-1. Transient Thermal Response Curve for SSP7N60B (t), T h e rm a l R e s p o n s e 10 0 D = 0 .5 0 .2 0 .1 0 .0 5 ※ N o te s : 1 . Z θ J C (t) = 2 .6 ℃ /W M a x . 2 . D u ty F a c to r, D = t 1 /t 2 3 . T J M - T C = P D M * Z θ J C (t) 10 -1 0 .0 2 0 .0 1 PDM t1 s in g le p u ls e Z θ JC t2 10 -2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ] Figure 11-2. Transient Thermal Response Curve for SSS7N60B ©2002 Fairchild Semiconductor Corporation Rev. B, June 2002 SSP7N60B/SSS7N60B Gate Charge Test Circuit & Waveform 50KΩ 12V 200nF 300nF Same Type as DUT VDS VGS Qg 10V Qgs Qgd VGS DUT 3mA Charge Resistive Switching Test Circuit & Waveforms VDS VGS RG RL VDD VDS 90% 10V DUT VGS 10% td(on) t on tr td(off) t off tf Unclamped Inductive Switching Test Circuit & Waveforms L VDS ID RG DUT tp BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD BVDSS IAS VDD VDD tp ID (t) VDS (t) Time 10V ©2002 Fairchild Semiconductor Corporation Rev. B, June 2002 SSP7N60B/SSS7N60B Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ I SD L Driver RG Same Type as DUT VDD VGS • dv/dt controlled by RG • ISD controlled by pulse period VGS ( Driver ) Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) IRM di/dt Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2002 Fairchild Semiconductor Corporation Rev. B, June 2002 SSP7N60B/SSS7N60B Package Dimensions TO-220 9.90 ±0.20 1.30 ±0.10 2.80 ±0.10 (8.70) ø3.60 ±0.10 (1.70) 4.50 ±0.20 1.30 –0.05 +0.10 9.20 ±0.20 (1.46) 13.08 ±0.20 (1.00) (3.00) 15.90 ±0.20 1.27 ±0.10 1.52 ±0.10 0.80 ±0.10 2.54TYP [2.54 ±0.20] 2.54TYP [2.54 ±0.20] 10.08 ±0.30 18.95MAX. (3.70) (45° ) 0.50 –0.05 +0.10 2.40 ±0.20 10.00 ±0.20 Dimensions in Millimeters ©2002 Fairchild Semiconductor Corporation Rev. B, June 2002 SSP7N60B/SSS7N60B Package Dimensions (Continued) TO-220F 3.30 ±0.10 10.16 ±0.20 (7.00) ø3.18 ±0.10 2.54 ±0.20 (0.70) 6.68 ±0.20 15.80 ±0.20 (1.00x45°) MAX1.47 9.75 ±0.30 0.80 ±0.10 (3 ) 0° 0.35 ±0.10 2.54TYP [2.54 ±0.20] #1 0.50 –0.05 2.54TYP [2.54 ±0.20] 4.70 ±0.20 +0.10 2.76 ±0.20 9.40 ±0.20 Dimensions in Millimeters ©2002 Fairchild Semiconductor Corporation Rev. B, June 2002 15.87 ±0.20 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DOME™ EcoSPARK™ E2CMOS™ EnSigna™ FACT™ FACT Quiet series™ FAST® FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ I2C™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC® OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench® QFET™ QS™ QT Optoelectronics™ Quiet Series™ SLIENT SWITCHER® SMART START™ SPM™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET® VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production ©2002 Fairchild Semiconductor Corporation Rev. H6 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT ™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST ® DISCLAIMER FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ I2C™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC ® OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench ® QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER ® SMART START™ SPM™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET ® VCX™ FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H7